guibuilder_pel7x64builder0
6 years ago
7 changed files with 442 additions and 25 deletions
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From 50426f3e177c383a2de1c22534171c12461164a3 Mon Sep 17 00:00:00 2001 |
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From: Matt Atwood <matthew.s.atwood@intel.com> |
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Date: Tue, 24 Apr 2018 12:42:39 -0700 |
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Subject: [PATCH libdrm] Intel: Add a Kaby Lake PCI ID |
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Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")' |
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v2: name change M -> ULX, add enumeration in KBL ULX |
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v3: add entry to IS_KABYLAKE |
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Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> |
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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--- |
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intel/intel_chipset.h | 6 ++++-- |
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1 file changed, 4 insertions(+), 2 deletions(-) |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index 01d250e8..ba2e3ac1 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -200,7 +200,8 @@ |
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#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 |
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#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 |
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#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E |
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-#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E |
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+#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E |
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+#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C |
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#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 |
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#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 |
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#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 |
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@@ -455,7 +456,8 @@ |
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#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ |
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- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ |
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+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ |
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+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ |
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(devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ |
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-- |
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2.17.1 |
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@ -0,0 +1,68 @@ |
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From 7164abebecfbf450cdc55133eb3162f8c1501ff3 Mon Sep 17 00:00:00 2001 |
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From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com> |
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Date: Tue, 19 Jun 2018 16:45:21 -0700 |
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Subject: [PATCH libdrm] intel: Introducing Amber Lake platform |
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MIME-Version: 1.0 |
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Content-Type: text/plain; charset=UTF-8 |
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Content-Transfer-Encoding: 8bit |
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Amber Lake uses the same gen graphics as Kaby Lake, including a id |
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that were previously marked as reserved on Kaby Lake, but that now is |
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moved to AML page. |
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So, let's just move it to AML macro that will feed into KBL macro |
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just to keep it better organized to make easier future code review |
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but it will be handled as a KBL. |
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This is a copy of merged i915's |
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commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") |
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: José Roberto de Souza <jose.souza@intel.com> |
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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--- |
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intel/intel_chipset.h | 9 ++++++--- |
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1 file changed, 6 insertions(+), 3 deletions(-) |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index 44e65f9e..583d6447 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -201,7 +201,6 @@ |
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#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 |
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#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E |
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#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E |
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-#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C |
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#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 |
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#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 |
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#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 |
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@@ -213,6 +212,9 @@ |
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#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A |
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#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D |
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+#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C |
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+#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 |
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+ |
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#define PCI_CHIP_BROXTON_0 0x0A84 |
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#define PCI_CHIP_BROXTON_1 0x1A84 |
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#define PCI_CHIP_BROXTON_2 0x5A84 |
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@@ -468,12 +470,13 @@ |
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#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ |
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- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ |
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(devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ |
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- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) |
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+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ |
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+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ |
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+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) |
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#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ |
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-- |
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2.17.1 |
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@ -0,0 +1,85 @@ |
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From 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 Mon Sep 17 00:00:00 2001 |
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From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com> |
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Date: Tue, 19 Jun 2018 16:45:20 -0700 |
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Subject: [PATCH libdrm] intel: Introducing Whiskey Lake platform |
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MIME-Version: 1.0 |
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Content-Type: text/plain; charset=UTF-8 |
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Content-Transfer-Encoding: 8bit |
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Whiskey Lake uses the same gen graphics as Coffe Lake, including some |
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ids that were previously marked as reserved on Coffe Lake, but that |
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now are moved to WHL page. |
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So, let's just move them to WHL macros that will feed into CFL macro |
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just to keep it better organized to make easier future code review |
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but it will be handled as a CFL. |
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This is a copy of merged i915's |
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commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") |
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: José Roberto de Souza <jose.souza@intel.com> |
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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--- |
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intel/intel_chipset.h | 33 +++++++++++++++++---------------- |
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1 file changed, 17 insertions(+), 16 deletions(-) |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index 32b2c48f..44e65f9e 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -231,16 +231,17 @@ |
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#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A |
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#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B |
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#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 |
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-#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 |
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-#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 |
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+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 |
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+ |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 |
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#define PCI_CHIP_CANNONLAKE_0 0x5A51 |
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#define PCI_CHIP_CANNONLAKE_1 0x5A59 |
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@@ -510,16 +511,16 @@ |
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#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) |
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-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ |
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+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) |
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#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ |
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IS_CFL_H(devid) || \ |
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-- |
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2.17.1 |
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@ -0,0 +1,107 @@ |
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From 1ac3ecde2f2c9afd7110389eccc6860daa6627ca Mon Sep 17 00:00:00 2001 |
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From: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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Date: Wed, 25 Apr 2018 17:09:37 -0700 |
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Subject: [PATCH libdrm] intel: add support for ICL 11 |
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Add the PCI IDs and the basic code to enable ICL. This is the current |
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PCI ID list in our documentation. |
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Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs") |
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v2: Michel provided a fix to IS_9XX that was broken by rebase bot. |
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v3: Fix double definition of PCI IDs, update IDs according to bspec |
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and keep them in the same order and rebase (Lucas) |
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Cc: Michel Thierry <michel.thierry@intel.com> |
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Reviewed-by: Michel Thierry <michel.thierry@intel.com> |
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Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> |
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--- |
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intel/intel_bufmgr_gem.c | 2 ++ |
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intel/intel_chipset.h | 27 ++++++++++++++++++++++++++- |
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intel/intel_decode.c | 4 +++- |
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3 files changed, 31 insertions(+), 2 deletions(-) |
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diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c |
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index 5c47a46f..8c3a4b20 100644 |
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--- a/intel/intel_bufmgr_gem.c |
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+++ b/intel/intel_bufmgr_gem.c |
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@@ -3660,6 +3660,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) |
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bufmgr_gem->gen = 9; |
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else if (IS_GEN10(bufmgr_gem->pci_device)) |
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bufmgr_gem->gen = 10; |
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+ else if (IS_GEN11(bufmgr_gem->pci_device)) |
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+ bufmgr_gem->gen = 11; |
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else { |
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free(bufmgr_gem); |
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bufmgr_gem = NULL; |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index ba2e3ac1..32b2c48f 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -257,6 +257,16 @@ |
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#define PCI_CHIP_CANNONLAKE_12 0x5A44 |
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#define PCI_CHIP_CANNONLAKE_13 0x5A4C |
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+#define PCI_CHIP_ICELAKE_11_0 0x8A50 |
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+#define PCI_CHIP_ICELAKE_11_1 0x8A51 |
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+#define PCI_CHIP_ICELAKE_11_2 0x8A5C |
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+#define PCI_CHIP_ICELAKE_11_3 0x8A5D |
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+#define PCI_CHIP_ICELAKE_11_4 0x8A52 |
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+#define PCI_CHIP_ICELAKE_11_5 0x8A5A |
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+#define PCI_CHIP_ICELAKE_11_6 0x8A5B |
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+#define PCI_CHIP_ICELAKE_11_7 0x8A71 |
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+#define PCI_CHIP_ICELAKE_11_8 0x8A70 |
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+ |
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
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(devid) == PCI_CHIP_I915_GM || \ |
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(devid) == PCI_CHIP_I945_GM || \ |
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@@ -538,6 +548,20 @@ |
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#define IS_GEN10(devid) (IS_CANNONLAKE(devid)) |
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+#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_1 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_2 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_3 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_4 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_5 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_6 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_7 || \ |
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+ (devid) == PCI_CHIP_ICELAKE_11_8) |
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+ |
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+#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid)) |
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+ |
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+#define IS_GEN11(devid) (IS_ICELAKE_11(devid)) |
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+ |
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#define IS_9XX(dev) (IS_GEN3(dev) || \ |
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IS_GEN4(dev) || \ |
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IS_GEN5(dev) || \ |
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@@ -545,6 +569,7 @@ |
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IS_GEN7(dev) || \ |
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IS_GEN8(dev) || \ |
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IS_GEN9(dev) || \ |
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- IS_GEN10(dev)) |
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+ IS_GEN10(dev) || \ |
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+ IS_GEN11(dev)) |
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#endif /* _INTEL_CHIPSET_H */ |
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diff --git a/intel/intel_decode.c b/intel/intel_decode.c |
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index bc7b04b8..b24861b1 100644 |
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--- a/intel/intel_decode.c |
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+++ b/intel/intel_decode.c |
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@@ -3823,7 +3823,9 @@ drm_intel_decode_context_alloc(uint32_t devid) |
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ctx->devid = devid; |
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ctx->out = stdout; |
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|
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|
- if (IS_GEN10(devid)) |
||||||
|
+ if (IS_GEN11(devid)) |
||||||
|
+ ctx->gen = 11; |
||||||
|
+ else if (IS_GEN10(devid)) |
||||||
|
ctx->gen = 10; |
||||||
|
else if (IS_GEN9(devid)) |
||||||
|
ctx->gen = 9; |
||||||
|
-- |
||||||
|
2.17.1 |
||||||
|
|
@ -0,0 +1,93 @@ |
|||||||
|
From 7b12381723021fd5fbcf761e6832dd16a14f52d4 Mon Sep 17 00:00:00 2001 |
||||||
|
From: Rodrigo Vivi <rodrigo.vivi@intel.com> |
||||||
|
Date: Wed, 7 Feb 2018 22:46:43 -0800 |
||||||
|
Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs. |
||||||
|
|
||||||
|
Let's sync CNL ids with Spec and kernel. |
||||||
|
|
||||||
|
Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: |
||||||
|
Add Cannonlake PCI IDs for another SKU.")' and |
||||||
|
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' |
||||||
|
|
||||||
|
Cc: James Ausmus <james.ausmus@intel.com> |
||||||
|
Cc: Lucas De Marchi <lucas.demarchi@intel.com> |
||||||
|
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> |
||||||
|
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
||||||
|
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> |
||||||
|
--- |
||||||
|
intel/intel_chipset.h | 52 +++++++++++++++++++++++-------------------- |
||||||
|
1 file changed, 28 insertions(+), 24 deletions(-) |
||||||
|
|
||||||
|
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
||||||
|
index 3818e71e..01d250e8 100644 |
||||||
|
--- a/intel/intel_chipset.h |
||||||
|
+++ b/intel/intel_chipset.h |
||||||
|
@@ -241,16 +241,20 @@ |
||||||
|
#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 |
||||||
|
#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 |
||||||
|
|
||||||
|
-#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A |
||||||
|
-#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 |
||||||
|
-#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_0 0x5A51 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_1 0x5A59 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_2 0x5A41 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_3 0x5A49 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_4 0x5A52 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_5 0x5A5A |
||||||
|
+#define PCI_CHIP_CANNONLAKE_6 0x5A42 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_7 0x5A4A |
||||||
|
+#define PCI_CHIP_CANNONLAKE_8 0x5A50 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_9 0x5A40 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_10 0x5A54 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_11 0x5A5C |
||||||
|
+#define PCI_CHIP_CANNONLAKE_12 0x5A44 |
||||||
|
+#define PCI_CHIP_CANNONLAKE_13 0x5A4C |
||||||
|
|
||||||
|
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
||||||
|
(devid) == PCI_CHIP_I915_GM || \ |
||||||
|
@@ -515,20 +519,20 @@ |
||||||
|
IS_GEMINILAKE(devid) || \ |
||||||
|
IS_COFFEELAKE(devid)) |
||||||
|
|
||||||
|
-#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) |
||||||
|
- |
||||||
|
-#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ |
||||||
|
- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) |
||||||
|
- |
||||||
|
-#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ |
||||||
|
- IS_CNL_Y(devid)) |
||||||
|
+#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_1 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_2 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_3 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_4 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_5 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_6 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_7 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_8 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_9 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_10 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_11 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_12 || \ |
||||||
|
+ (devid) == PCI_CHIP_CANNONLAKE_13) |
||||||
|
|
||||||
|
#define IS_GEN10(devid) (IS_CANNONLAKE(devid)) |
||||||
|
|
||||||
|
-- |
||||||
|
2.17.1 |
||||||
|
|
@ -1,22 +1,31 @@ |
|||||||
#!/bin/sh |
#!/bin/sh |
||||||
|
|
||||||
# Usage: ./make-git-snapshot.sh [COMMIT] |
proto=$1 |
||||||
# |
branch=$2 |
||||||
# to make a snapshot of the given tag/branch. Defaults to HEAD. |
|
||||||
# Point env var REF to a local mesa repo to reduce clone time. |
|
||||||
|
|
||||||
DIRNAME=xf86-video-intel-$( date +%Y%m%d ) |
if [ -z "$proto" ]; then |
||||||
|
echo "Usage: $0 <proto name> [<branch>]" |
||||||
|
exit 1 |
||||||
|
fi |
||||||
|
|
||||||
echo REF ${REF:+--reference $REF} |
dirname=$proto-$( date +%Y%m%d ) |
||||||
echo DIRNAME $DIRNAME |
|
||||||
echo HEAD ${1:-HEAD} |
|
||||||
|
|
||||||
rm -rf $DIRNAME |
rm -rf $dirname |
||||||
|
git clone git://git.freedesktop.org/git/xorg/proto/$proto $dirname |
||||||
|
cd $dirname |
||||||
|
if [ -z "$branch" ]; then |
||||||
|
git log | head -1 |
||||||
|
else |
||||||
|
git checkout $branch |
||||||
|
fi |
||||||
|
sha=`git rev-list --max-count=1 --abbrev-commit HEAD` |
||||||
|
git repack -a -d |
||||||
|
cd .. |
||||||
|
|
||||||
git clone ${REF:+--reference $REF} \ |
# append sha to dirname |
||||||
git://git.freedesktop.org/git/xorg/driver/xf86-video-intel $DIRNAME |
mv $dirname $dirname-git$sha |
||||||
|
dirname=$dirname-git$sha |
||||||
GIT_DIR=$DIRNAME/.git git archive --format=tar --prefix=$DIRNAME/ ${1:-HEAD} \ |
tarball=$dirname.tar.bz2 |
||||||
| bzip2 > $DIRNAME.tar.bz2 |
tar jcf $tarball $dirname |
||||||
|
rm -rf $dirname |
||||||
# rm -rf $DIRNAME |
echo "$tarball is now available" |
||||||
|
Loading…
Reference in new issue