From 450d5080dc7e17556916af05c75d39da76cd0494 Mon Sep 17 00:00:00 2001 From: guibuilder_pel7x64builder0 Date: Sun, 25 Nov 2018 21:40:43 +0100 Subject: [PATCH] libdrm package update Signed-off-by: guibuilder_pel7x64builder0 --- .../0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch | 44 +++++++ ...ntel-Introducing-Amber-Lake-platform.patch | 68 +++++++++++ ...el-Introducing-Whiskey-Lake-platform.patch | 85 ++++++++++++++ .../0001-intel-add-support-for-ICL-11.patch | 107 ++++++++++++++++++ ...-intel_chipset.h-Sync-Cannonlake-IDs.patch | 93 +++++++++++++++ SOURCES/make-git-snapshot.sh | 41 ++++--- SPECS/libdrm.spec | 29 +++-- 7 files changed, 442 insertions(+), 25 deletions(-) create mode 100644 SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch create mode 100644 SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch create mode 100644 SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch create mode 100644 SOURCES/0001-intel-add-support-for-ICL-11.patch create mode 100644 SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch diff --git a/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch b/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch new file mode 100644 index 0000000..d07e93f --- /dev/null +++ b/SOURCES/0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch @@ -0,0 +1,44 @@ +From 50426f3e177c383a2de1c22534171c12461164a3 Mon Sep 17 00:00:00 2001 +From: Matt Atwood +Date: Tue, 24 Apr 2018 12:42:39 -0700 +Subject: [PATCH libdrm] Intel: Add a Kaby Lake PCI ID + +Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")' + +v2: name change M -> ULX, add enumeration in KBL ULX +v3: add entry to IS_KABYLAKE + +Signed-off-by: Matt Atwood +Reviewed-by: Rodrigo Vivi +Signed-off-by: Rodrigo Vivi +--- + intel/intel_chipset.h | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h +index 01d250e8..ba2e3ac1 100644 +--- a/intel/intel_chipset.h ++++ b/intel/intel_chipset.h +@@ -200,7 +200,8 @@ + #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 + #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 + #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E +-#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E ++#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E ++#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C + #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 + #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 + #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +@@ -455,7 +456,8 @@ + + #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ +- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ ++ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ ++ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ +-- +2.17.1 + diff --git a/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch b/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch new file mode 100644 index 0000000..8d3d731 --- /dev/null +++ b/SOURCES/0001-intel-Introducing-Amber-Lake-platform.patch @@ -0,0 +1,68 @@ +From 7164abebecfbf450cdc55133eb3162f8c1501ff3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= +Date: Tue, 19 Jun 2018 16:45:21 -0700 +Subject: [PATCH libdrm] intel: Introducing Amber Lake platform +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Amber Lake uses the same gen graphics as Kaby Lake, including a id +that were previously marked as reserved on Kaby Lake, but that now is +moved to AML page. + +So, let's just move it to AML macro that will feed into KBL macro +just to keep it better organized to make easier future code review +but it will be handled as a KBL. + +This is a copy of merged i915's +commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") + +Cc: Rodrigo Vivi +Signed-off-by: José Roberto de Souza +Reviewed-by: Rodrigo Vivi +Signed-off-by: Rodrigo Vivi +--- + intel/intel_chipset.h | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h +index 44e65f9e..583d6447 100644 +--- a/intel/intel_chipset.h ++++ b/intel/intel_chipset.h +@@ -201,7 +201,6 @@ + #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 + #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E + #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E +-#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C + #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 + #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 + #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +@@ -213,6 +212,9 @@ + #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A + #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D + ++#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C ++#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 ++ + #define PCI_CHIP_BROXTON_0 0x0A84 + #define PCI_CHIP_BROXTON_1 0x1A84 + #define PCI_CHIP_BROXTON_2 0x5A84 +@@ -468,12 +470,13 @@ + #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ +- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ +- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) ++ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ ++ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ ++ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) + + #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ +-- +2.17.1 + diff --git a/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch b/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch new file mode 100644 index 0000000..4a7cd8d --- /dev/null +++ b/SOURCES/0001-intel-Introducing-Whiskey-Lake-platform.patch @@ -0,0 +1,85 @@ +From 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= +Date: Tue, 19 Jun 2018 16:45:20 -0700 +Subject: [PATCH libdrm] intel: Introducing Whiskey Lake platform +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Whiskey Lake uses the same gen graphics as Coffe Lake, including some +ids that were previously marked as reserved on Coffe Lake, but that +now are moved to WHL page. + +So, let's just move them to WHL macros that will feed into CFL macro +just to keep it better organized to make easier future code review +but it will be handled as a CFL. + +This is a copy of merged i915's +commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") + +Cc: Rodrigo Vivi +Signed-off-by: José Roberto de Souza +Reviewed-by: Rodrigo Vivi +Signed-off-by: Rodrigo Vivi +--- + intel/intel_chipset.h | 33 +++++++++++++++++---------------- + 1 file changed, 17 insertions(+), 16 deletions(-) + +diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h +index 32b2c48f..44e65f9e 100644 +--- a/intel/intel_chipset.h ++++ b/intel/intel_chipset.h +@@ -231,16 +231,17 @@ + #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A + #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B + #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 +-#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 +-#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 +-#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 +-#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 +-#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 +-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 +-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 +-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 +-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 +-#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 ++#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 ++#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 ++#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 ++#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 ++#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 ++ ++#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 ++#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 ++#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 ++#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 ++#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 + + #define PCI_CHIP_CANNONLAKE_0 0x5A51 + #define PCI_CHIP_CANNONLAKE_1 0x5A59 +@@ -510,16 +511,16 @@ + #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) + +-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ +- (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ +- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ +- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ +- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ ++#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ +- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) ++ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ ++ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ ++ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ ++ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ ++ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) + + #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ + IS_CFL_H(devid) || \ +-- +2.17.1 + diff --git a/SOURCES/0001-intel-add-support-for-ICL-11.patch b/SOURCES/0001-intel-add-support-for-ICL-11.patch new file mode 100644 index 0000000..6eb1fa0 --- /dev/null +++ b/SOURCES/0001-intel-add-support-for-ICL-11.patch @@ -0,0 +1,107 @@ +From 1ac3ecde2f2c9afd7110389eccc6860daa6627ca Mon Sep 17 00:00:00 2001 +From: Paulo Zanoni +Date: Wed, 25 Apr 2018 17:09:37 -0700 +Subject: [PATCH libdrm] intel: add support for ICL 11 + +Add the PCI IDs and the basic code to enable ICL. This is the current +PCI ID list in our documentation. + +Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs") + +v2: Michel provided a fix to IS_9XX that was broken by rebase bot. +v3: Fix double definition of PCI IDs, update IDs according to bspec + and keep them in the same order and rebase (Lucas) + +Cc: Michel Thierry +Reviewed-by: Michel Thierry +Signed-off-by: Paulo Zanoni +Signed-off-by: Rodrigo Vivi +Signed-off-by: Lucas De Marchi +--- + intel/intel_bufmgr_gem.c | 2 ++ + intel/intel_chipset.h | 27 ++++++++++++++++++++++++++- + intel/intel_decode.c | 4 +++- + 3 files changed, 31 insertions(+), 2 deletions(-) + +diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c +index 5c47a46f..8c3a4b20 100644 +--- a/intel/intel_bufmgr_gem.c ++++ b/intel/intel_bufmgr_gem.c +@@ -3660,6 +3660,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) + bufmgr_gem->gen = 9; + else if (IS_GEN10(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 10; ++ else if (IS_GEN11(bufmgr_gem->pci_device)) ++ bufmgr_gem->gen = 11; + else { + free(bufmgr_gem); + bufmgr_gem = NULL; +diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h +index ba2e3ac1..32b2c48f 100644 +--- a/intel/intel_chipset.h ++++ b/intel/intel_chipset.h +@@ -257,6 +257,16 @@ + #define PCI_CHIP_CANNONLAKE_12 0x5A44 + #define PCI_CHIP_CANNONLAKE_13 0x5A4C + ++#define PCI_CHIP_ICELAKE_11_0 0x8A50 ++#define PCI_CHIP_ICELAKE_11_1 0x8A51 ++#define PCI_CHIP_ICELAKE_11_2 0x8A5C ++#define PCI_CHIP_ICELAKE_11_3 0x8A5D ++#define PCI_CHIP_ICELAKE_11_4 0x8A52 ++#define PCI_CHIP_ICELAKE_11_5 0x8A5A ++#define PCI_CHIP_ICELAKE_11_6 0x8A5B ++#define PCI_CHIP_ICELAKE_11_7 0x8A71 ++#define PCI_CHIP_ICELAKE_11_8 0x8A70 ++ + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ + (devid) == PCI_CHIP_I915_GM || \ + (devid) == PCI_CHIP_I945_GM || \ +@@ -538,6 +548,20 @@ + + #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) + ++#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_1 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_2 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_3 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_4 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_5 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_6 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_7 || \ ++ (devid) == PCI_CHIP_ICELAKE_11_8) ++ ++#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid)) ++ ++#define IS_GEN11(devid) (IS_ICELAKE_11(devid)) ++ + #define IS_9XX(dev) (IS_GEN3(dev) || \ + IS_GEN4(dev) || \ + IS_GEN5(dev) || \ +@@ -545,6 +569,7 @@ + IS_GEN7(dev) || \ + IS_GEN8(dev) || \ + IS_GEN9(dev) || \ +- IS_GEN10(dev)) ++ IS_GEN10(dev) || \ ++ IS_GEN11(dev)) + + #endif /* _INTEL_CHIPSET_H */ +diff --git a/intel/intel_decode.c b/intel/intel_decode.c +index bc7b04b8..b24861b1 100644 +--- a/intel/intel_decode.c ++++ b/intel/intel_decode.c +@@ -3823,7 +3823,9 @@ drm_intel_decode_context_alloc(uint32_t devid) + ctx->devid = devid; + ctx->out = stdout; + +- if (IS_GEN10(devid)) ++ if (IS_GEN11(devid)) ++ ctx->gen = 11; ++ else if (IS_GEN10(devid)) + ctx->gen = 10; + else if (IS_GEN9(devid)) + ctx->gen = 9; +-- +2.17.1 + diff --git a/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch b/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch new file mode 100644 index 0000000..6ad7e37 --- /dev/null +++ b/SOURCES/0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch @@ -0,0 +1,93 @@ +From 7b12381723021fd5fbcf761e6832dd16a14f52d4 Mon Sep 17 00:00:00 2001 +From: Rodrigo Vivi +Date: Wed, 7 Feb 2018 22:46:43 -0800 +Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs. + +Let's sync CNL ids with Spec and kernel. + +Sync with kernel commit '3f43031b1693 ("drm/i915/cnl: +Add Cannonlake PCI IDs for another SKU.")' and +commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")' + +Cc: James Ausmus +Cc: Lucas De Marchi +Cc: Paulo Zanoni +Signed-off-by: Rodrigo Vivi +Reviewed-by: Rafael Antognolli +--- + intel/intel_chipset.h | 52 +++++++++++++++++++++++-------------------- + 1 file changed, 28 insertions(+), 24 deletions(-) + +diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h +index 3818e71e..01d250e8 100644 +--- a/intel/intel_chipset.h ++++ b/intel/intel_chipset.h +@@ -241,16 +241,20 @@ + #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 + #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 + +-#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 +-#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A +-#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 +-#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A +-#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 +-#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 +-#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 +-#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 +-#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 +-#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 ++#define PCI_CHIP_CANNONLAKE_0 0x5A51 ++#define PCI_CHIP_CANNONLAKE_1 0x5A59 ++#define PCI_CHIP_CANNONLAKE_2 0x5A41 ++#define PCI_CHIP_CANNONLAKE_3 0x5A49 ++#define PCI_CHIP_CANNONLAKE_4 0x5A52 ++#define PCI_CHIP_CANNONLAKE_5 0x5A5A ++#define PCI_CHIP_CANNONLAKE_6 0x5A42 ++#define PCI_CHIP_CANNONLAKE_7 0x5A4A ++#define PCI_CHIP_CANNONLAKE_8 0x5A50 ++#define PCI_CHIP_CANNONLAKE_9 0x5A40 ++#define PCI_CHIP_CANNONLAKE_10 0x5A54 ++#define PCI_CHIP_CANNONLAKE_11 0x5A5C ++#define PCI_CHIP_CANNONLAKE_12 0x5A44 ++#define PCI_CHIP_CANNONLAKE_13 0x5A4C + + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ + (devid) == PCI_CHIP_I915_GM || \ +@@ -515,20 +519,20 @@ + IS_GEMINILAKE(devid) || \ + IS_COFFEELAKE(devid)) + +-#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ +- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ +- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ +- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ +- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ +- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) +- +-#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ +- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ +- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ +- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) +- +-#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ +- IS_CNL_Y(devid)) ++#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_1 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_2 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_3 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_4 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_5 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_6 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_7 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_8 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_9 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_10 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_11 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_12 || \ ++ (devid) == PCI_CHIP_CANNONLAKE_13) + + #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) + +-- +2.17.1 + diff --git a/SOURCES/make-git-snapshot.sh b/SOURCES/make-git-snapshot.sh index 4d1ec9f..64a5bec 100755 --- a/SOURCES/make-git-snapshot.sh +++ b/SOURCES/make-git-snapshot.sh @@ -1,22 +1,31 @@ #!/bin/sh -# Usage: ./make-git-snapshot.sh [COMMIT] -# -# to make a snapshot of the given tag/branch. Defaults to HEAD. -# Point env var REF to a local mesa repo to reduce clone time. +proto=$1 +branch=$2 -DIRNAME=xf86-video-intel-$( date +%Y%m%d ) +if [ -z "$proto" ]; then + echo "Usage: $0 []" + exit 1 +fi -echo REF ${REF:+--reference $REF} -echo DIRNAME $DIRNAME -echo HEAD ${1:-HEAD} +dirname=$proto-$( date +%Y%m%d ) -rm -rf $DIRNAME +rm -rf $dirname +git clone git://git.freedesktop.org/git/xorg/proto/$proto $dirname +cd $dirname +if [ -z "$branch" ]; then + git log | head -1 +else + git checkout $branch +fi +sha=`git rev-list --max-count=1 --abbrev-commit HEAD` +git repack -a -d +cd .. -git clone ${REF:+--reference $REF} \ - git://git.freedesktop.org/git/xorg/driver/xf86-video-intel $DIRNAME - -GIT_DIR=$DIRNAME/.git git archive --format=tar --prefix=$DIRNAME/ ${1:-HEAD} \ - | bzip2 > $DIRNAME.tar.bz2 - -# rm -rf $DIRNAME +# append sha to dirname +mv $dirname $dirname-git$sha +dirname=$dirname-git$sha +tarball=$dirname.tar.bz2 +tar jcf $tarball $dirname +rm -rf $dirname +echo "$tarball is now available" diff --git a/SPECS/libdrm.spec b/SPECS/libdrm.spec index ec1566b..4d5ff6a 100644 --- a/SPECS/libdrm.spec +++ b/SPECS/libdrm.spec @@ -2,15 +2,15 @@ Summary: Direct Rendering Manager runtime library Name: libdrm -Version: 2.4.83 -Release: 2%{?dist} +Version: 2.4.91 +Release: 3%{?dist} License: MIT Group: System Environment/Libraries URL: http://dri.sourceforge.net %if 0%{?gitdate} Source0: %{name}-%{gitdate}.tar.bz2 %else -Source0: http://dri.freedesktop.org/libdrm/%{name}-%{version}.tar.bz2 +Source0: https://dri.freedesktop.org/libdrm/%{name}-%{version}.tar.bz2 %endif Source1: make-git-snapshot.sh @@ -34,8 +34,6 @@ BuildRequires: xorg-x11-util-macros Source2: 91-drm-modeset.rules -# backport from upstream master seems like it should be in here. -Patch1: 0001-intel-Change-a-KBL-pci-id-to-GT2-from-GT1.5.patch # hardcode the 666 instead of 660 for device nodes Patch3: libdrm-make-dri-perms-okay.patch # remove backwards compat not needed on Fedora @@ -43,8 +41,12 @@ Patch4: libdrm-2.4.0-no-bc.patch # make rule to print the list of test programs Patch5: libdrm-2.4.25-check-programs.patch -#Backport some intel pci ids. -Patch10: 0002-intel-Add-more-Coffeelake-PCI-IDs.patch +# backport new intel pci-ids +Patch10: 0001-intel-intel_chipset.h-Sync-Cannonlake-IDs.patch +Patch11: 0001-Intel-Add-a-Kaby-Lake-PCI-ID.patch +Patch12: 0001-intel-add-support-for-ICL-11.patch +Patch13: 0001-intel-Introducing-Whiskey-Lake-platform.patch +Patch14: 0001-intel-Introducing-Amber-Lake-platform.patch %description Direct Rendering Manager runtime library @@ -69,12 +71,15 @@ Utility programs for the kernel DRM interface. Will void your warranty. %prep %setup -q %{?gitdate:-n %{name}-%{gitdate}} -%patch1 -p1 -b .intelfix %patch3 -p1 -b .forceperms %patch4 -p1 -b .no-bc %patch5 -p1 -b .check -%patch10 -p1 -b .cfl +%patch10 -p1 +%patch11 -p1 +%patch12 -p1 +%patch13 -p1 +%patch14 -p1 %build autoreconf -v --install || exit 1 @@ -238,6 +243,12 @@ done %{_mandir}/man7/drm*.7* %changelog +* Wed Aug 22 2018 Rob Clark - 2.4.91-3 +- Add WHL, AML, etc PCI IDs + +* Tue Apr 24 2018 Adam Jackson - 2.4.91-2 +- libdrm 2.4.91 + * Fri Jan 12 2018 Dave Airlie - 2.4.83-2 - Add some Coffeelake PCI IDs