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428 lines
15 KiB
428 lines
15 KiB
From cfbf97cb54a6d06a80e86c85869331e4e2871129 Mon Sep 17 00:00:00 2001 |
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From: Ilya Leoshkevich <iii@linux.ibm.com> |
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Date: Thu, 19 Mar 2020 11:52:03 +0100 |
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Subject: [PATCH] s390x: vectorize crc32 |
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|
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Use vector extensions when compiling for s390x and binutils knows |
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about them. At runtime, check whether kernel supports vector |
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extensions (it has to be not just the CPU, but also the kernel) and |
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choose between the regular and the vectorized implementations. |
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--- |
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Makefile.in | 9 ++ |
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configure | 28 +++++ |
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contrib/gcc/zifunc.h | 21 +++- |
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contrib/s390/crc32-vx.c | 195 ++++++++++++++++++++++++++++++++ |
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contrib/s390/crc32_z_resolver.c | 41 +++++++ |
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crc32.c | 11 +- |
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6 files changed, 301 insertions(+), 4 deletions(-) |
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create mode 100644 contrib/s390/crc32-vx.c |
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create mode 100644 contrib/s390/crc32_z_resolver.c |
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diff --git a/Makefile.in b/Makefile.in |
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index d392616..63f76da 100644 |
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--- a/Makefile.in |
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+++ b/Makefile.in |
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@@ -29,6 +29,7 @@ LDFLAGS= |
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TEST_LDFLAGS=-L. libz.a |
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LDSHARED=$(CC) |
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CPP=$(CC) -E |
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+VGFMAFLAG= |
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STATICLIB=libz.a |
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SHAREDLIB=libz.so |
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@@ -179,6 +180,9 @@ crc32.o: $(SRCDIR)crc32.c |
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crc32_z_power8.o: $(SRCDIR)contrib/power/crc32_z_power8.c |
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$(CC) $(CFLAGS) -mcpu=power8 $(ZINC) -c -o $@ $(SRCDIR)contrib/power/crc32_z_power8.c |
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|
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+crc32-vx.o: $(SRCDIR)contrib/s390/crc32-vx.c |
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+ $(CC) $(CFLAGS) $(VGFMAFLAG) $(ZINC) -c -o $@ $(SRCDIR)contrib/s390/crc32-vx.c |
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+ |
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deflate.o: $(SRCDIR)deflate.c |
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$(CC) $(CFLAGS) $(ZINC) -c -o $@ $(SRCDIR)deflate.c |
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|
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@@ -229,6 +233,11 @@ crc32.lo: $(SRCDIR)crc32.c |
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$(CC) $(SFLAGS) $(ZINC) -DPIC -c -o objs/crc32.o $(SRCDIR)crc32.c |
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-@mv objs/crc32.o $@ |
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|
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+crc32-vx.lo: $(SRCDIR)contrib/s390/crc32-vx.c |
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+ -@mkdir objs 2>/dev/null || test -d objs |
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+ $(CC) $(SFLAGS) $(VGFMAFLAG) $(ZINC) -DPIC -c -o objs/crc32-vx.o $(SRCDIR)contrib/s390/crc32-vx.c |
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+ -@mv objs/crc32-vx.o $@ |
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+ |
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crc32_z_power8.lo: $(SRCDIR)contrib/power/crc32_z_power8.c |
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-@mkdir objs 2>/dev/null || test -d objs |
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$(CC) $(SFLAGS) -mcpu=power8 $(ZINC) -DPIC -c -o objs/crc32_z_power8.o $(SRCDIR)contrib/power/crc32_z_power8.c |
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diff --git a/configure b/configure |
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index e37dac8..a4606b8 100755 |
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--- a/configure |
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+++ b/configure |
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@@ -915,6 +915,32 @@ else |
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echo "Checking for Power optimizations support... No." | tee -a configure.log |
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fi |
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+# check if we are compiling for s390 and binutils support vector extensions |
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+VGFMAFLAG=-march=z13 |
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+cat > $test.c <<EOF |
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+#ifndef __s390__ |
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+#error |
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+#endif |
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+EOF |
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+if try $CC -c $CFLAGS $VGFMAFLAG $test.c; then |
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+ CFLAGS="$CFLAGS -DHAVE_S390X_VX" |
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+ SFLAGS="$SFLAGS -DHAVE_S390X_VX" |
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+ OBJC="$OBJC crc32-vx.o" |
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+ PIC_OBJC="$PIC_OBJC crc32-vx.lo" |
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+ echo "Checking for s390 vector extensions... Yes." | tee -a configure.log |
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+ |
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+ for flag in -mzarch -fzvector; do |
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+ if try $CC -c $CFLAGS $VGFMAFLAG $flag $test.c; then |
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+ VGFMAFLAG="$VGFMAFLAG $flag" |
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+ echo "Checking for $flag... Yes." | tee -a configure.log |
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+ else |
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+ echo "Checking for $flag... No." | tee -a configure.log |
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+ fi |
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+ done |
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+else |
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+ echo "Checking for s390 vector extensions... No." | tee -a configure.log |
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+fi |
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+ |
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# show the results in the log |
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echo >> configure.log |
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echo ALL = $ALL >> configure.log |
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@@ -947,6 +973,7 @@ echo mandir = $mandir >> configure.log |
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echo prefix = $prefix >> configure.log |
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echo sharedlibdir = $sharedlibdir >> configure.log |
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echo uname = $uname >> configure.log |
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+echo VGFMAFLAG = $VGFMAFLAG >> configure.log |
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|
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# udpate Makefile with the configure results |
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sed < ${SRCDIR}Makefile.in " |
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@@ -956,6 +983,7 @@ sed < ${SRCDIR}Makefile.in " |
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/^LDFLAGS *=/s#=.*#=$LDFLAGS# |
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/^LDSHARED *=/s#=.*#=$LDSHARED# |
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/^CPP *=/s#=.*#=$CPP# |
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+/^VGFMAFLAG *=/s#=.*#=$VGFMAFLAG# |
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/^STATICLIB *=/s#=.*#=$STATICLIB# |
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/^SHAREDLIB *=/s#=.*#=$SHAREDLIB# |
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/^SHAREDLIBV *=/s#=.*#=$SHAREDLIBV# |
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diff --git a/contrib/gcc/zifunc.h b/contrib/gcc/zifunc.h |
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index daf4fe4..b62379e 100644 |
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--- a/contrib/gcc/zifunc.h |
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+++ b/contrib/gcc/zifunc.h |
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@@ -8,9 +8,28 @@ |
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/* Helpers for arch optimizations */ |
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+#if defined(__clang__) |
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+#if __has_feature(coverage_sanitizer) |
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+#define Z_IFUNC_NO_SANCOV __attribute__((no_sanitize("coverage"))) |
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+#else /* __has_feature(coverage_sanitizer) */ |
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+#define Z_IFUNC_NO_SANCOV |
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+#endif /* __has_feature(coverage_sanitizer) */ |
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+#else /* __clang__ */ |
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+#define Z_IFUNC_NO_SANCOV |
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+#endif /* __clang__ */ |
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+ |
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+#ifdef __s390__ |
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+#define Z_IFUNC_PARAMS unsigned long hwcap |
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+#define Z_IFUNC_ATTRS Z_IFUNC_NO_SANCOV |
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+#else /* __s390__ */ |
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+#define Z_IFUNC_PARAMS void |
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+#define Z_IFUNC_ATTRS |
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+#endif /* __s390__ */ |
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+ |
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#define Z_IFUNC(fname) \ |
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typeof(fname) fname __attribute__ ((ifunc (#fname "_resolver"))); \ |
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- local typeof(fname) *fname##_resolver(void) |
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+ Z_IFUNC_ATTRS \ |
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+ local typeof(fname) *fname##_resolver(Z_IFUNC_PARAMS) |
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/* This is a helper macro to declare a resolver for an indirect function |
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* (ifunc). Let's say you have function |
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* |
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diff --git a/contrib/s390/crc32-vx.c b/contrib/s390/crc32-vx.c |
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new file mode 100644 |
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index 0000000..fa5387c |
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--- /dev/null |
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+++ b/contrib/s390/crc32-vx.c |
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@@ -0,0 +1,195 @@ |
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+/* |
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+ * Hardware-accelerated CRC-32 variants for Linux on z Systems |
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+ * |
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+ * Use the z/Architecture Vector Extension Facility to accelerate the |
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+ * computing of bitreflected CRC-32 checksums. |
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+ * |
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+ * This CRC-32 implementation algorithm is bitreflected and processes |
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+ * the least-significant bit first (Little-Endian). |
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+ * |
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+ * This code was originally written by Hendrik Brueckner |
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+ * <brueckner@linux.vnet.ibm.com> for use in the Linux kernel and has been |
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+ * relicensed under the zlib license. |
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+ */ |
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+ |
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+#include "../../zutil.h" |
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+ |
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+#include <stdint.h> |
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+#include <vecintrin.h> |
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+ |
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+typedef unsigned char uv16qi __attribute__((vector_size(16))); |
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+typedef unsigned int uv4si __attribute__((vector_size(16))); |
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+typedef unsigned long long uv2di __attribute__((vector_size(16))); |
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+ |
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+uint32_t crc32_le_vgfm_16(uint32_t crc, const unsigned char *buf, size_t len) { |
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+ /* |
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+ * The CRC-32 constant block contains reduction constants to fold and |
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+ * process particular chunks of the input data stream in parallel. |
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+ * |
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+ * For the CRC-32 variants, the constants are precomputed according to |
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+ * these definitions: |
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+ * |
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+ * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1 |
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+ * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1 |
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+ * R3 = [(x128+32 mod P'(x) << 32)]' << 1 |
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+ * R4 = [(x128-32 mod P'(x) << 32)]' << 1 |
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+ * R5 = [(x64 mod P'(x) << 32)]' << 1 |
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+ * R6 = [(x32 mod P'(x) << 32)]' << 1 |
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+ * |
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+ * The bitreflected Barret reduction constant, u', is defined as |
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+ * the bit reversal of floor(x**64 / P(x)). |
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+ * |
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+ * where P(x) is the polynomial in the normal domain and the P'(x) is the |
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+ * polynomial in the reversed (bitreflected) domain. |
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+ * |
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+ * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials: |
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+ * |
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+ * P(x) = 0x04C11DB7 |
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+ * P'(x) = 0xEDB88320 |
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+ */ |
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+ const uv16qi perm_le2be = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}; /* BE->LE mask */ |
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+ const uv2di r2r1 = {0x1C6E41596, 0x154442BD4}; /* R2, R1 */ |
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+ const uv2di r4r3 = {0x0CCAA009E, 0x1751997D0}; /* R4, R3 */ |
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+ const uv2di r5 = {0, 0x163CD6124}; /* R5 */ |
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+ const uv2di ru_poly = {0, 0x1F7011641}; /* u' */ |
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+ const uv2di crc_poly = {0, 0x1DB710641}; /* P'(x) << 1 */ |
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+ |
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+ /* |
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+ * Load the initial CRC value. |
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+ * |
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+ * The CRC value is loaded into the rightmost word of the |
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+ * vector register and is later XORed with the LSB portion |
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+ * of the loaded input data. |
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+ */ |
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+ uv2di v0 = {0, 0}; |
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+ v0 = (uv2di)vec_insert(crc, (uv4si)v0, 3); |
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+ |
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+ /* Load a 64-byte data chunk and XOR with CRC */ |
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+ uv2di v1 = vec_perm(((uv2di *)buf)[0], ((uv2di *)buf)[0], perm_le2be); |
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+ uv2di v2 = vec_perm(((uv2di *)buf)[1], ((uv2di *)buf)[1], perm_le2be); |
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+ uv2di v3 = vec_perm(((uv2di *)buf)[2], ((uv2di *)buf)[2], perm_le2be); |
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+ uv2di v4 = vec_perm(((uv2di *)buf)[3], ((uv2di *)buf)[3], perm_le2be); |
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+ |
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+ v1 ^= v0; |
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+ buf += 64; |
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+ len -= 64; |
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+ |
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+ while (len >= 64) { |
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+ /* Load the next 64-byte data chunk */ |
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+ uv16qi part1 = vec_perm(((uv16qi *)buf)[0], ((uv16qi *)buf)[0], perm_le2be); |
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+ uv16qi part2 = vec_perm(((uv16qi *)buf)[1], ((uv16qi *)buf)[1], perm_le2be); |
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+ uv16qi part3 = vec_perm(((uv16qi *)buf)[2], ((uv16qi *)buf)[2], perm_le2be); |
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+ uv16qi part4 = vec_perm(((uv16qi *)buf)[3], ((uv16qi *)buf)[3], perm_le2be); |
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+ |
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+ /* |
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+ * Perform a GF(2) multiplication of the doublewords in V1 with |
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+ * the R1 and R2 reduction constants in V0. The intermediate result |
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+ * is then folded (accumulated) with the next data chunk in PART1 and |
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+ * stored in V1. Repeat this step for the register contents |
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+ * in V2, V3, and V4 respectively. |
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+ */ |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r2r1, v1, part1); |
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+ v2 = (uv2di)vec_gfmsum_accum_128(r2r1, v2, part2); |
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+ v3 = (uv2di)vec_gfmsum_accum_128(r2r1, v3, part3); |
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+ v4 = (uv2di)vec_gfmsum_accum_128(r2r1, v4, part4); |
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+ |
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+ buf += 64; |
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+ len -= 64; |
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+ } |
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+ |
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+ /* |
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+ * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3 |
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+ * and R4 and accumulating the next 128-bit chunk until a single 128-bit |
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+ * value remains. |
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+ */ |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r4r3, v1, (uv16qi)v2); |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r4r3, v1, (uv16qi)v3); |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r4r3, v1, (uv16qi)v4); |
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+ |
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+ while (len >= 16) { |
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+ /* Load next data chunk */ |
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+ v2 = vec_perm(*(uv2di *)buf, *(uv2di *)buf, perm_le2be); |
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+ |
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+ /* Fold next data chunk */ |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r4r3, v1, (uv16qi)v2); |
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+ |
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+ buf += 16; |
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+ len -= 16; |
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+ } |
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+ |
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+ /* |
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+ * Set up a vector register for byte shifts. The shift value must |
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+ * be loaded in bits 1-4 in byte element 7 of a vector register. |
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+ * Shift by 8 bytes: 0x40 |
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+ * Shift by 4 bytes: 0x20 |
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+ */ |
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+ uv16qi v9 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; |
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+ v9 = vec_insert((unsigned char)0x40, v9, 7); |
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+ |
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+ /* |
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+ * Prepare V0 for the next GF(2) multiplication: shift V0 by 8 bytes |
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+ * to move R4 into the rightmost doubleword and set the leftmost |
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+ * doubleword to 0x1. |
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+ */ |
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+ v0 = vec_srb(r4r3, (uv2di)v9); |
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+ v0[0] = 1; |
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+ |
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+ /* |
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+ * Compute GF(2) product of V1 and V0. The rightmost doubleword |
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+ * of V1 is multiplied with R4. The leftmost doubleword of V1 is |
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+ * multiplied by 0x1 and is then XORed with rightmost product. |
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+ * Implicitly, the intermediate leftmost product becomes padded |
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+ */ |
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+ v1 = (uv2di)vec_gfmsum_128(v0, v1); |
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+ |
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+ /* |
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+ * Now do the final 32-bit fold by multiplying the rightmost word |
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+ * in V1 with R5 and XOR the result with the remaining bits in V1. |
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+ * |
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+ * To achieve this by a single VGFMAG, right shift V1 by a word |
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+ * and store the result in V2 which is then accumulated. Use the |
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+ * vector unpack instruction to load the rightmost half of the |
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+ * doubleword into the rightmost doubleword element of V1; the other |
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+ * half is loaded in the leftmost doubleword. |
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+ * The vector register with CONST_R5 contains the R5 constant in the |
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+ * rightmost doubleword and the leftmost doubleword is zero to ignore |
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+ * the leftmost product of V1. |
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+ */ |
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+ v9 = vec_insert((unsigned char)0x20, v9, 7); |
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+ v2 = vec_srb(v1, (uv2di)v9); |
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+ v1 = vec_unpackl((uv4si)v1); /* Split rightmost doubleword */ |
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+ v1 = (uv2di)vec_gfmsum_accum_128(r5, v1, (uv16qi)v2); |
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+ |
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+ /* |
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+ * Apply a Barret reduction to compute the final 32-bit CRC value. |
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+ * |
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+ * The input values to the Barret reduction are the degree-63 polynomial |
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+ * in V1 (R(x)), degree-32 generator polynomial, and the reduction |
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+ * constant u. The Barret reduction result is the CRC value of R(x) mod |
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+ * P(x). |
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+ * |
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+ * The Barret reduction algorithm is defined as: |
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+ * |
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+ * 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u |
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+ * 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x) |
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+ * 3. C(x) = R(x) XOR T2(x) mod x^32 |
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+ * |
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+ * Note: The leftmost doubleword of vector register containing |
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+ * CONST_RU_POLY is zero and, thus, the intermediate GF(2) product |
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+ * is zero and does not contribute to the final result. |
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+ */ |
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+ |
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+ /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */ |
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+ v2 = vec_unpackl((uv4si)v1); |
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+ v2 = (uv2di)vec_gfmsum_128(ru_poly, v2); |
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+ |
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+ /* |
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+ * Compute the GF(2) product of the CRC polynomial with T1(x) in |
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+ * V2 and XOR the intermediate result, T2(x), with the value in V1. |
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+ * The final result is stored in word element 2 of V2. |
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+ */ |
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+ v2 = vec_unpackl((uv4si)v2); |
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+ v2 = (uv2di)vec_gfmsum_accum_128(crc_poly, v2, (uv16qi)v1); |
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+ |
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+ return ((uv4si)v2)[2]; |
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+} |
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diff --git a/contrib/s390/crc32_z_resolver.c b/contrib/s390/crc32_z_resolver.c |
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new file mode 100644 |
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index 0000000..9749cab |
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--- /dev/null |
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+++ b/contrib/s390/crc32_z_resolver.c |
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@@ -0,0 +1,41 @@ |
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+#include <sys/auxv.h> |
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+#include "../gcc/zifunc.h" |
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+ |
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+#define VX_MIN_LEN 64 |
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+#define VX_ALIGNMENT 16L |
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+#define VX_ALIGN_MASK (VX_ALIGNMENT - 1) |
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+ |
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+unsigned int crc32_le_vgfm_16(unsigned int crc, const unsigned char FAR *buf, z_size_t len); |
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+ |
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+local unsigned long s390_crc32_vx(unsigned long crc, const unsigned char FAR *buf, z_size_t len) |
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+{ |
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+ uintptr_t prealign, aligned, remaining; |
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+ |
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+ if (buf == Z_NULL) return 0UL; |
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+ |
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+ if (len < VX_MIN_LEN + VX_ALIGN_MASK) |
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+ return crc32_z_default(crc, buf, len); |
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+ |
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+ if ((uintptr_t)buf & VX_ALIGN_MASK) { |
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+ prealign = VX_ALIGNMENT - ((uintptr_t)buf & VX_ALIGN_MASK); |
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+ len -= prealign; |
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+ crc = crc32_z_default(crc, buf, prealign); |
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+ buf += prealign; |
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+ } |
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+ aligned = len & ~VX_ALIGN_MASK; |
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+ remaining = len & VX_ALIGN_MASK; |
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+ |
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+ crc = crc32_le_vgfm_16(crc ^ 0xffffffff, buf, (size_t)aligned) ^ 0xffffffff; |
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+ |
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+ if (remaining) |
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+ crc = crc32_z_default(crc, buf + aligned, remaining); |
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+ |
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+ return crc; |
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+} |
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+ |
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+Z_IFUNC(crc32_z) |
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+{ |
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+ if (hwcap & HWCAP_S390_VX) |
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+ return s390_crc32_vx; |
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+ return crc32_z_default; |
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+} |
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diff --git a/crc32.c b/crc32.c |
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index b0cda20..379fac3 100644 |
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--- a/crc32.c |
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+++ b/crc32.c |
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@@ -199,12 +199,12 @@ const z_crc_t FAR * ZEXPORT get_crc_table() |
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#define DO8 DO1; DO1; DO1; DO1; DO1; DO1; DO1; DO1 |
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|
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/* ========================================================================= */ |
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-#ifdef Z_POWER_OPT |
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+#if defined(Z_POWER_OPT) || defined(HAVE_S390X_VX) |
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/* Rename function so resolver can use its symbol. The default version will be |
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* returned by the resolver if the host has no support for an optimized version. |
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*/ |
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#define crc32_z crc32_z_default |
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-#endif /* Z_POWER_OPT */ |
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+#endif /* defined(Z_POWER_OPT) || defined(HAVE_S390X_VX) */ |
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|
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unsigned long ZEXPORT crc32_z(crc, buf, len) |
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unsigned long crc; |
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@@ -240,10 +240,15 @@ unsigned long ZEXPORT crc32_z(crc, buf, len) |
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return crc ^ 0xffffffffUL; |
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} |
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|
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-#ifdef Z_POWER_OPT |
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+#if defined(Z_POWER_OPT) || defined(HAVE_S390X_VX) |
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#undef crc32_z |
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+#ifdef Z_POWER_OPT |
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#include "contrib/power/crc32_z_resolver.c" |
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#endif /* Z_POWER_OPT */ |
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+#ifdef HAVE_S390X_VX |
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+#include "contrib/s390/crc32_z_resolver.c" |
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+#endif /* HAVE_S390X_VX */ |
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+#endif /* defined(Z_POWER_OPT) || defined(HAVE_S390X_VX) */ |
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|
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/* ========================================================================= */ |
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unsigned long ZEXPORT crc32(crc, buf, len) |
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-- |
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2.39.1 |
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