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261 lines
7.5 KiB
261 lines
7.5 KiB
commit 103a469dc7755fd9e8ccf362f3dd4c55dc761908 |
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Author: Sajan Karumanchi <sajan.karumanchi@amd.com> |
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Date: Wed Jan 18 18:29:04 2023 +0100 |
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x86: Cache computation for AMD architecture. |
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All AMD architectures cache details will be computed based on |
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__cpuid__ `0x8000_001D` and the reference to __cpuid__ `0x8000_0006` will be |
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zeroed out for future architectures. |
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Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com> |
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h |
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index 8f85f70858413ebe..a7d2cc5fef03884b 100644 |
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--- a/sysdeps/x86/dl-cacheinfo.h |
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+++ b/sysdeps/x86/dl-cacheinfo.h |
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@@ -311,117 +311,47 @@ handle_intel (int name, const struct cpu_features *cpu_features) |
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static long int __attribute__ ((noinline)) |
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-handle_amd (int name) |
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+handle_amd (int name, const struct cpu_features *cpu_features) |
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{ |
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unsigned int eax; |
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unsigned int ebx; |
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unsigned int ecx; |
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unsigned int edx; |
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- __cpuid (0x80000000, eax, ebx, ecx, edx); |
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+ unsigned int count = 0x1; |
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/* No level 4 cache (yet). */ |
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if (name > _SC_LEVEL3_CACHE_LINESIZE) |
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return 0; |
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- unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE); |
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- if (eax < fn) |
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- return 0; |
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- |
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- __cpuid (fn, eax, ebx, ecx, edx); |
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+ if (name >= _SC_LEVEL3_CACHE_SIZE) |
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+ count = 0x3; |
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+ else if (name >= _SC_LEVEL2_CACHE_SIZE) |
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+ count = 0x2; |
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+ else if (name >= _SC_LEVEL1_DCACHE_SIZE) |
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+ count = 0x0; |
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- if (name < _SC_LEVEL1_DCACHE_SIZE) |
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- { |
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- name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE; |
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- ecx = edx; |
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- } |
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+ __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx); |
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switch (name) |
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{ |
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- case _SC_LEVEL1_DCACHE_SIZE: |
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- return (ecx >> 14) & 0x3fc00; |
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- |
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- case _SC_LEVEL1_DCACHE_ASSOC: |
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- ecx >>= 16; |
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- if ((ecx & 0xff) == 0xff) |
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- /* Fully associative. */ |
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- return (ecx << 2) & 0x3fc00; |
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- return ecx & 0xff; |
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- |
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- case _SC_LEVEL1_DCACHE_LINESIZE: |
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- return ecx & 0xff; |
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- |
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- case _SC_LEVEL2_CACHE_SIZE: |
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- return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00; |
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- |
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- case _SC_LEVEL2_CACHE_ASSOC: |
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- switch ((ecx >> 12) & 0xf) |
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- { |
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- case 0: |
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- case 1: |
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- case 2: |
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- case 4: |
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- return (ecx >> 12) & 0xf; |
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- case 6: |
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- return 8; |
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- case 8: |
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- return 16; |
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- case 10: |
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- return 32; |
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- case 11: |
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- return 48; |
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- case 12: |
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- return 64; |
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- case 13: |
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- return 96; |
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- case 14: |
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- return 128; |
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- case 15: |
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- return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff); |
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- default: |
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- return 0; |
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- } |
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- /* NOTREACHED */ |
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- |
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- case _SC_LEVEL2_CACHE_LINESIZE: |
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- return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff; |
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- |
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- case _SC_LEVEL3_CACHE_SIZE: |
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- return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1; |
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- |
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- case _SC_LEVEL3_CACHE_ASSOC: |
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- switch ((edx >> 12) & 0xf) |
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- { |
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- case 0: |
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- case 1: |
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- case 2: |
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- case 4: |
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- return (edx >> 12) & 0xf; |
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- case 6: |
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- return 8; |
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- case 8: |
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- return 16; |
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- case 10: |
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- return 32; |
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- case 11: |
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- return 48; |
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- case 12: |
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- return 64; |
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- case 13: |
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- return 96; |
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- case 14: |
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- return 128; |
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- case 15: |
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- return ((edx & 0x3ffc0000) << 1) / (edx & 0xff); |
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- default: |
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- return 0; |
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- } |
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- /* NOTREACHED */ |
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- |
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- case _SC_LEVEL3_CACHE_LINESIZE: |
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- return (edx & 0xf000) == 0 ? 0 : edx & 0xff; |
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- |
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- default: |
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- assert (! "cannot happen"); |
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+ case _SC_LEVEL1_ICACHE_ASSOC: |
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+ case _SC_LEVEL1_DCACHE_ASSOC: |
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+ case _SC_LEVEL2_CACHE_ASSOC: |
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+ case _SC_LEVEL3_CACHE_ASSOC: |
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+ return ecx?((ebx >> 22) & 0x3ff) + 1 : 0; |
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+ case _SC_LEVEL1_ICACHE_LINESIZE: |
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+ case _SC_LEVEL1_DCACHE_LINESIZE: |
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+ case _SC_LEVEL2_CACHE_LINESIZE: |
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+ case _SC_LEVEL3_CACHE_LINESIZE: |
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+ return ecx?(ebx & 0xfff) + 1 : 0; |
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+ case _SC_LEVEL1_ICACHE_SIZE: |
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+ case _SC_LEVEL1_DCACHE_SIZE: |
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+ case _SC_LEVEL2_CACHE_SIZE: |
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+ case _SC_LEVEL3_CACHE_SIZE: |
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+ return ecx?(((ebx >> 22) & 0x3ff) + 1)*((ebx & 0xfff) + 1)\ |
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+ *(ecx + 1):0; |
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+ default: |
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+ assert (! "cannot happen"); |
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} |
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return -1; |
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} |
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@@ -698,10 +628,6 @@ static void |
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dl_init_cacheinfo (struct cpu_features *cpu_features) |
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{ |
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/* Find out what brand of processor. */ |
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- unsigned int ebx; |
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- unsigned int ecx; |
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- unsigned int edx; |
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- int max_cpuid_ex; |
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long int data = -1; |
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long int shared = -1; |
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long int core = -1; |
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@@ -771,70 +697,30 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) |
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} |
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else if (cpu_features->basic.kind == arch_kind_amd) |
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{ |
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- data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); |
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- core = handle_amd (_SC_LEVEL2_CACHE_SIZE); |
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- shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); |
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+ data = handle_amd (_SC_LEVEL1_DCACHE_SIZE, cpu_features); |
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+ core = handle_amd (_SC_LEVEL2_CACHE_SIZE, cpu_features); |
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+ shared = handle_amd (_SC_LEVEL3_CACHE_SIZE, cpu_features); |
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- level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); |
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- level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE); |
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+ level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE, cpu_features); |
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+ level1_icache_linesize |
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+ = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features); |
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level1_dcache_size = data; |
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- level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); |
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- level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); |
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+ level1_dcache_assoc |
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+ = handle_amd (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); |
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+ level1_dcache_linesize |
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+ = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); |
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level2_cache_size = core; |
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- level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); |
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- level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); |
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+ level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC, cpu_features); |
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+ level2_cache_linesize |
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+ = handle_amd (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); |
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level3_cache_size = shared; |
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- level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); |
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- level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); |
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- |
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- /* Get maximum extended function. */ |
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- __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx); |
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+ level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC, cpu_features); |
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+ level3_cache_linesize |
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+ = handle_amd (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); |
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if (shared <= 0) |
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- /* No shared L3 cache. All we have is the L2 cache. */ |
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- shared = core; |
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- else |
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- { |
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- /* Figure out the number of logical threads that share L3. */ |
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- if (max_cpuid_ex >= 0x80000008) |
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- { |
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- /* Get width of APIC ID. */ |
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- __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx); |
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- threads = 1 << ((ecx >> 12) & 0x0f); |
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- } |
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- |
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- if (threads == 0 || cpu_features->basic.family >= 0x17) |
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- { |
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- /* If APIC ID width is not available, use logical |
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- processor count. */ |
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- __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx); |
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- |
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- if ((edx & (1 << 28)) != 0) |
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- threads = (ebx >> 16) & 0xff; |
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- } |
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- |
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- /* Cap usage of highest cache level to the number of |
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- supported threads. */ |
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- if (threads > 0) |
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- shared /= threads; |
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- |
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- /* Get shared cache per ccx for Zen architectures. */ |
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- if (cpu_features->basic.family >= 0x17) |
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- { |
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- unsigned int eax; |
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- |
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- /* Get number of threads share the L3 cache in CCX. */ |
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- __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx); |
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- |
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- unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1; |
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- shared *= threads_per_ccx; |
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- } |
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- else |
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- { |
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- /* Account for exclusive L2 and L3 caches. */ |
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- shared += core; |
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- } |
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- } |
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+ /* No shared L3 cache. All we have is the L2 cache. */ |
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+ shared = core; |
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} |
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cpu_features->level1_icache_size = level1_icache_size;
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