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843 lines
25 KiB
843 lines
25 KiB
commit a7392db2ff2b9dd906500941ac6361dbe2211b0d |
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Author: Noah Goldstein <goldstein.w.n@gmail.com> |
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Date: Mon Nov 1 00:49:51 2021 -0500 |
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x86: Optimize memmove-vec-unaligned-erms.S |
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No bug. |
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The optimizations are as follows: |
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1) Always align entry to 64 bytes. This makes behavior more |
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predictable and makes other frontend optimizations easier. |
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2) Make the L(more_8x_vec) cases 4k aliasing aware. This can have |
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significant benefits in the case that: |
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0 < (dst - src) < [256, 512] |
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3) Align before `rep movsb`. For ERMS this is roughly a [0, 30%] |
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improvement and for FSRM [-10%, 25%]. |
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In addition to these primary changes there is general cleanup |
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throughout to optimize the aligning routines and control flow logic. |
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Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com> |
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com> |
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(cherry picked from commit a6b7502ec0c2da89a7437f43171f160d713e39c6) |
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diff --git a/sysdeps/x86_64/memmove.S b/sysdeps/x86_64/memmove.S |
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index db106a7a1f23f268..b2b318084823dceb 100644 |
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--- a/sysdeps/x86_64/memmove.S |
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+++ b/sysdeps/x86_64/memmove.S |
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@@ -25,7 +25,7 @@ |
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/* Use movups and movaps for smaller code sizes. */ |
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#define VMOVU movups |
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#define VMOVA movaps |
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- |
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+#define MOV_SIZE 3 |
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#define SECTION(p) p |
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#ifdef USE_MULTIARCH |
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diff --git a/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms-rtm.S b/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms-rtm.S |
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index 1ec1962e861dbf63..67a55f0c85af841c 100644 |
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--- a/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms-rtm.S |
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+++ b/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms-rtm.S |
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@@ -4,7 +4,7 @@ |
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# define VMOVNT vmovntdq |
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# define VMOVU vmovdqu |
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# define VMOVA vmovdqa |
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- |
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+# define MOV_SIZE 4 |
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# define ZERO_UPPER_VEC_REGISTERS_RETURN \ |
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ZERO_UPPER_VEC_REGISTERS_RETURN_XTEST |
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diff --git a/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S |
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index e195e93f153c9512..975ae6c0515b83cb 100644 |
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--- a/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S |
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+++ b/sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S |
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@@ -4,7 +4,7 @@ |
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# define VMOVNT vmovntdq |
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# define VMOVU vmovdqu |
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# define VMOVA vmovdqa |
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- |
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+# define MOV_SIZE 4 |
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# define SECTION(p) p##.avx |
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# define MEMMOVE_SYMBOL(p,s) p##_avx_##s |
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diff --git a/sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S |
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index 848848ab39ff9326..0fa7126830af7acb 100644 |
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--- a/sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S |
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+++ b/sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S |
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@@ -25,7 +25,7 @@ |
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# define VMOVU vmovdqu64 |
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# define VMOVA vmovdqa64 |
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# define VZEROUPPER |
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- |
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+# define MOV_SIZE 6 |
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# define SECTION(p) p##.evex512 |
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# define MEMMOVE_SYMBOL(p,s) p##_avx512_##s |
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diff --git a/sysdeps/x86_64/multiarch/memmove-evex-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-evex-unaligned-erms.S |
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index 0cbce8f944da51a0..88715441feaaccf5 100644 |
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--- a/sysdeps/x86_64/multiarch/memmove-evex-unaligned-erms.S |
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+++ b/sysdeps/x86_64/multiarch/memmove-evex-unaligned-erms.S |
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@@ -25,7 +25,7 @@ |
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# define VMOVU vmovdqu64 |
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# define VMOVA vmovdqa64 |
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# define VZEROUPPER |
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- |
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+# define MOV_SIZE 6 |
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# define SECTION(p) p##.evex |
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# define MEMMOVE_SYMBOL(p,s) p##_evex_##s |
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diff --git a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S |
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index abde8438d41f2320..7b27cbdda5fb99f7 100644 |
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--- a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S |
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+++ b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S |
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@@ -76,6 +76,25 @@ |
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# endif |
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#endif |
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+/* Whether to align before movsb. Ultimately we want 64 byte |
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+ align and not worth it to load 4x VEC for VEC_SIZE == 16. */ |
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+#define ALIGN_MOVSB (VEC_SIZE > 16) |
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+/* Number of bytes to align movsb to. */ |
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+#define MOVSB_ALIGN_TO 64 |
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+ |
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+#define SMALL_MOV_SIZE (MOV_SIZE <= 4) |
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+#define LARGE_MOV_SIZE (MOV_SIZE > 4) |
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+ |
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+#if SMALL_MOV_SIZE + LARGE_MOV_SIZE != 1 |
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+# error MOV_SIZE Unknown |
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+#endif |
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+ |
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+#if LARGE_MOV_SIZE |
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+# define SMALL_SIZE_OFFSET (4) |
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+#else |
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+# define SMALL_SIZE_OFFSET (0) |
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+#endif |
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+ |
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#ifndef PAGE_SIZE |
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# define PAGE_SIZE 4096 |
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#endif |
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@@ -199,25 +218,21 @@ L(start): |
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# endif |
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cmp $VEC_SIZE, %RDX_LP |
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jb L(less_vec) |
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+ /* Load regardless. */ |
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+ VMOVU (%rsi), %VEC(0) |
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cmp $(VEC_SIZE * 2), %RDX_LP |
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ja L(more_2x_vec) |
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-#if !defined USE_MULTIARCH || !IS_IN (libc) |
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-L(last_2x_vec): |
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-#endif |
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */ |
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- VMOVU (%rsi), %VEC(0) |
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VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(1) |
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VMOVU %VEC(0), (%rdi) |
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VMOVU %VEC(1), -VEC_SIZE(%rdi,%rdx) |
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-#if !defined USE_MULTIARCH || !IS_IN (libc) |
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-L(nop): |
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- ret |
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+#if !(defined USE_MULTIARCH && IS_IN (libc)) |
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+ ZERO_UPPER_VEC_REGISTERS_RETURN |
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#else |
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VZEROUPPER_RETURN |
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#endif |
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#if defined USE_MULTIARCH && IS_IN (libc) |
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END (MEMMOVE_SYMBOL (__memmove, unaligned)) |
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- |
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# if VEC_SIZE == 16 |
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ENTRY (__mempcpy_chk_erms) |
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cmp %RDX_LP, %RCX_LP |
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@@ -289,7 +304,7 @@ ENTRY (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned_erms)) |
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END (MEMMOVE_CHK_SYMBOL (__memmove_chk, unaligned_erms)) |
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# endif |
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-ENTRY (MEMMOVE_SYMBOL (__memmove, unaligned_erms)) |
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+ENTRY_P2ALIGN (MEMMOVE_SYMBOL (__memmove, unaligned_erms), 6) |
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movq %rdi, %rax |
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L(start_erms): |
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# ifdef __ILP32__ |
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@@ -298,310 +313,448 @@ L(start_erms): |
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# endif |
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cmp $VEC_SIZE, %RDX_LP |
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jb L(less_vec) |
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+ /* Load regardless. */ |
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+ VMOVU (%rsi), %VEC(0) |
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cmp $(VEC_SIZE * 2), %RDX_LP |
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ja L(movsb_more_2x_vec) |
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-L(last_2x_vec): |
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- /* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */ |
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- VMOVU (%rsi), %VEC(0) |
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- VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(1) |
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+ /* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. |
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+ */ |
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+ VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(1) |
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VMOVU %VEC(0), (%rdi) |
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- VMOVU %VEC(1), -VEC_SIZE(%rdi,%rdx) |
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+ VMOVU %VEC(1), -VEC_SIZE(%rdi, %rdx) |
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L(return): |
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-#if VEC_SIZE > 16 |
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+# if VEC_SIZE > 16 |
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ZERO_UPPER_VEC_REGISTERS_RETURN |
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-#else |
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+# else |
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ret |
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+# endif |
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#endif |
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-L(movsb): |
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- cmp __x86_rep_movsb_stop_threshold(%rip), %RDX_LP |
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- jae L(more_8x_vec) |
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- cmpq %rsi, %rdi |
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- jb 1f |
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- /* Source == destination is less common. */ |
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- je L(nop) |
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- leaq (%rsi,%rdx), %r9 |
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- cmpq %r9, %rdi |
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- /* Avoid slow backward REP MOVSB. */ |
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- jb L(more_8x_vec_backward) |
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-# if AVOID_SHORT_DISTANCE_REP_MOVSB |
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- testl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, __x86_string_control(%rip) |
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- jz 3f |
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- movq %rdi, %rcx |
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- subq %rsi, %rcx |
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- jmp 2f |
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-# endif |
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-1: |
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-# if AVOID_SHORT_DISTANCE_REP_MOVSB |
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- testl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, __x86_string_control(%rip) |
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- jz 3f |
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- movq %rsi, %rcx |
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- subq %rdi, %rcx |
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-2: |
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-/* Avoid "rep movsb" if RCX, the distance between source and destination, |
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- is N*4GB + [1..63] with N >= 0. */ |
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- cmpl $63, %ecx |
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- jbe L(more_2x_vec) /* Avoid "rep movsb" if ECX <= 63. */ |
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-3: |
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-# endif |
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- mov %RDX_LP, %RCX_LP |
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- rep movsb |
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-L(nop): |
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+#if LARGE_MOV_SIZE |
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+ /* If LARGE_MOV_SIZE this fits in the aligning bytes between the |
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+ ENTRY block and L(less_vec). */ |
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+ .p2align 4,, 8 |
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+L(between_4_7): |
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+ /* From 4 to 7. No branch when size == 4. */ |
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+ movl (%rsi), %ecx |
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+ movl (%rsi, %rdx), %esi |
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+ movl %ecx, (%rdi) |
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+ movl %esi, (%rdi, %rdx) |
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ret |
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#endif |
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+ .p2align 4 |
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L(less_vec): |
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/* Less than 1 VEC. */ |
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#if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64 |
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# error Unsupported VEC_SIZE! |
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#endif |
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#if VEC_SIZE > 32 |
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- cmpb $32, %dl |
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+ cmpl $32, %edx |
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jae L(between_32_63) |
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#endif |
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#if VEC_SIZE > 16 |
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- cmpb $16, %dl |
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+ cmpl $16, %edx |
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jae L(between_16_31) |
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#endif |
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- cmpb $8, %dl |
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+ cmpl $8, %edx |
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jae L(between_8_15) |
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- cmpb $4, %dl |
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+#if SMALL_MOV_SIZE |
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+ cmpl $4, %edx |
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+#else |
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+ subq $4, %rdx |
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+#endif |
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jae L(between_4_7) |
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- cmpb $1, %dl |
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- ja L(between_2_3) |
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- jb 1f |
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- movzbl (%rsi), %ecx |
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+ cmpl $(1 - SMALL_SIZE_OFFSET), %edx |
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+ jl L(copy_0) |
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+ movb (%rsi), %cl |
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+ je L(copy_1) |
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+ movzwl (-2 + SMALL_SIZE_OFFSET)(%rsi, %rdx), %esi |
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+ movw %si, (-2 + SMALL_SIZE_OFFSET)(%rdi, %rdx) |
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+L(copy_1): |
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movb %cl, (%rdi) |
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-1: |
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+L(copy_0): |
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ret |
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+ |
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+#if SMALL_MOV_SIZE |
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+ .p2align 4,, 8 |
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+L(between_4_7): |
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+ /* From 4 to 7. No branch when size == 4. */ |
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+ movl -4(%rsi, %rdx), %ecx |
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+ movl (%rsi), %esi |
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+ movl %ecx, -4(%rdi, %rdx) |
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+ movl %esi, (%rdi) |
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+ ret |
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+#endif |
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+ |
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+#if VEC_SIZE > 16 |
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+ /* From 16 to 31. No branch when size == 16. */ |
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+ .p2align 4,, 8 |
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+L(between_16_31): |
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+ vmovdqu (%rsi), %xmm0 |
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+ vmovdqu -16(%rsi, %rdx), %xmm1 |
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+ vmovdqu %xmm0, (%rdi) |
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+ vmovdqu %xmm1, -16(%rdi, %rdx) |
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+ /* No ymm registers have been touched. */ |
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+ ret |
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+#endif |
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+ |
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#if VEC_SIZE > 32 |
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+ .p2align 4,, 10 |
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L(between_32_63): |
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/* From 32 to 63. No branch when size == 32. */ |
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VMOVU (%rsi), %YMM0 |
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- VMOVU -32(%rsi,%rdx), %YMM1 |
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+ VMOVU -32(%rsi, %rdx), %YMM1 |
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VMOVU %YMM0, (%rdi) |
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- VMOVU %YMM1, -32(%rdi,%rdx) |
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- VZEROUPPER_RETURN |
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-#endif |
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-#if VEC_SIZE > 16 |
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- /* From 16 to 31. No branch when size == 16. */ |
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-L(between_16_31): |
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- VMOVU (%rsi), %XMM0 |
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- VMOVU -16(%rsi,%rdx), %XMM1 |
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- VMOVU %XMM0, (%rdi) |
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- VMOVU %XMM1, -16(%rdi,%rdx) |
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+ VMOVU %YMM1, -32(%rdi, %rdx) |
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VZEROUPPER_RETURN |
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#endif |
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+ |
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+ .p2align 4,, 10 |
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L(between_8_15): |
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/* From 8 to 15. No branch when size == 8. */ |
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- movq -8(%rsi,%rdx), %rcx |
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+ movq -8(%rsi, %rdx), %rcx |
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movq (%rsi), %rsi |
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- movq %rcx, -8(%rdi,%rdx) |
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movq %rsi, (%rdi) |
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+ movq %rcx, -8(%rdi, %rdx) |
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ret |
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-L(between_4_7): |
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- /* From 4 to 7. No branch when size == 4. */ |
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- movl -4(%rsi,%rdx), %ecx |
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- movl (%rsi), %esi |
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- movl %ecx, -4(%rdi,%rdx) |
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- movl %esi, (%rdi) |
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- ret |
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-L(between_2_3): |
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- /* From 2 to 3. No branch when size == 2. */ |
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- movzwl -2(%rsi,%rdx), %ecx |
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- movzwl (%rsi), %esi |
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- movw %cx, -2(%rdi,%rdx) |
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- movw %si, (%rdi) |
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- ret |
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+ .p2align 4,, 10 |
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+L(last_4x_vec): |
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+ /* Copy from 2 * VEC + 1 to 4 * VEC, inclusively. */ |
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+ |
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+ /* VEC(0) and VEC(1) have already been loaded. */ |
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+ VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(2) |
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+ VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VEC(3) |
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+ VMOVU %VEC(0), (%rdi) |
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+ VMOVU %VEC(1), VEC_SIZE(%rdi) |
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+ VMOVU %VEC(2), -VEC_SIZE(%rdi, %rdx) |
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+ VMOVU %VEC(3), -(VEC_SIZE * 2)(%rdi, %rdx) |
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+ VZEROUPPER_RETURN |
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+ |
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+ .p2align 4 |
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#if defined USE_MULTIARCH && IS_IN (libc) |
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L(movsb_more_2x_vec): |
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cmp __x86_rep_movsb_threshold(%rip), %RDX_LP |
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ja L(movsb) |
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#endif |
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L(more_2x_vec): |
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- /* More than 2 * VEC and there may be overlap between destination |
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- and source. */ |
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+ /* More than 2 * VEC and there may be overlap between |
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+ destination and source. */ |
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cmpq $(VEC_SIZE * 8), %rdx |
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ja L(more_8x_vec) |
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+ /* Load VEC(1) regardless. VEC(0) has already been loaded. */ |
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+ VMOVU VEC_SIZE(%rsi), %VEC(1) |
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cmpq $(VEC_SIZE * 4), %rdx |
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jbe L(last_4x_vec) |
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- /* Copy from 4 * VEC + 1 to 8 * VEC, inclusively. */ |
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- VMOVU (%rsi), %VEC(0) |
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- VMOVU VEC_SIZE(%rsi), %VEC(1) |
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+ /* Copy from 4 * VEC + 1 to 8 * VEC, inclusively. */ |
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VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2) |
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VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3) |
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- VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(4) |
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- VMOVU -(VEC_SIZE * 2)(%rsi,%rdx), %VEC(5) |
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- VMOVU -(VEC_SIZE * 3)(%rsi,%rdx), %VEC(6) |
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- VMOVU -(VEC_SIZE * 4)(%rsi,%rdx), %VEC(7) |
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+ VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(4) |
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+ VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VEC(5) |
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+ VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %VEC(6) |
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+ VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %VEC(7) |
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VMOVU %VEC(0), (%rdi) |
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VMOVU %VEC(1), VEC_SIZE(%rdi) |
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VMOVU %VEC(2), (VEC_SIZE * 2)(%rdi) |
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VMOVU %VEC(3), (VEC_SIZE * 3)(%rdi) |
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- VMOVU %VEC(4), -VEC_SIZE(%rdi,%rdx) |
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- VMOVU %VEC(5), -(VEC_SIZE * 2)(%rdi,%rdx) |
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- VMOVU %VEC(6), -(VEC_SIZE * 3)(%rdi,%rdx) |
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- VMOVU %VEC(7), -(VEC_SIZE * 4)(%rdi,%rdx) |
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- VZEROUPPER_RETURN |
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-L(last_4x_vec): |
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- /* Copy from 2 * VEC + 1 to 4 * VEC, inclusively. */ |
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- VMOVU (%rsi), %VEC(0) |
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- VMOVU VEC_SIZE(%rsi), %VEC(1) |
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- VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(2) |
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- VMOVU -(VEC_SIZE * 2)(%rsi,%rdx), %VEC(3) |
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- VMOVU %VEC(0), (%rdi) |
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- VMOVU %VEC(1), VEC_SIZE(%rdi) |
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- VMOVU %VEC(2), -VEC_SIZE(%rdi,%rdx) |
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- VMOVU %VEC(3), -(VEC_SIZE * 2)(%rdi,%rdx) |
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+ VMOVU %VEC(4), -VEC_SIZE(%rdi, %rdx) |
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+ VMOVU %VEC(5), -(VEC_SIZE * 2)(%rdi, %rdx) |
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+ VMOVU %VEC(6), -(VEC_SIZE * 3)(%rdi, %rdx) |
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+ VMOVU %VEC(7), -(VEC_SIZE * 4)(%rdi, %rdx) |
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VZEROUPPER_RETURN |
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|
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+ .p2align 4,, 4 |
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L(more_8x_vec): |
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+ movq %rdi, %rcx |
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+ subq %rsi, %rcx |
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+ /* Go to backwards temporal copy if overlap no matter what as |
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+ backward REP MOVSB is slow and we don't want to use NT stores if |
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+ there is overlap. */ |
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+ cmpq %rdx, %rcx |
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+ /* L(more_8x_vec_backward_check_nop) checks for src == dst. */ |
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+ jb L(more_8x_vec_backward_check_nop) |
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/* Check if non-temporal move candidate. */ |
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#if (defined USE_MULTIARCH || VEC_SIZE == 16) && IS_IN (libc) |
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/* Check non-temporal store threshold. */ |
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- cmp __x86_shared_non_temporal_threshold(%rip), %RDX_LP |
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+ cmp __x86_shared_non_temporal_threshold(%rip), %RDX_LP |
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ja L(large_memcpy_2x) |
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#endif |
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- /* Entry if rdx is greater than non-temporal threshold but there |
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- is overlap. */ |
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+ /* To reach this point there cannot be overlap and dst > src. So |
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+ check for overlap and src > dst in which case correctness |
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+ requires forward copy. Otherwise decide between backward/forward |
|
+ copy depending on address aliasing. */ |
|
+ |
|
+ /* Entry if rdx is greater than __x86_rep_movsb_stop_threshold |
|
+ but less than __x86_shared_non_temporal_threshold. */ |
|
L(more_8x_vec_check): |
|
- cmpq %rsi, %rdi |
|
- ja L(more_8x_vec_backward) |
|
- /* Source == destination is less common. */ |
|
- je L(nop) |
|
- /* Load the first VEC and last 4 * VEC to support overlapping |
|
- addresses. */ |
|
- VMOVU (%rsi), %VEC(4) |
|
+ /* rcx contains dst - src. Add back length (rdx). */ |
|
+ leaq (%rcx, %rdx), %r8 |
|
+ /* If r8 has different sign than rcx then there is overlap so we |
|
+ must do forward copy. */ |
|
+ xorq %rcx, %r8 |
|
+ /* Isolate just sign bit of r8. */ |
|
+ shrq $63, %r8 |
|
+ /* Get 4k difference dst - src. */ |
|
+ andl $(PAGE_SIZE - 256), %ecx |
|
+ /* If r8 is non-zero must do foward for correctness. Otherwise |
|
+ if ecx is non-zero there is 4k False Alaising so do backward |
|
+ copy. */ |
|
+ addl %r8d, %ecx |
|
+ jz L(more_8x_vec_backward) |
|
+ |
|
+ /* if rdx is greater than __x86_shared_non_temporal_threshold |
|
+ but there is overlap, or from short distance movsb. */ |
|
+L(more_8x_vec_forward): |
|
+ /* Load first and last 4 * VEC to support overlapping addresses. |
|
+ */ |
|
+ |
|
+ /* First vec was already loaded into VEC(0). */ |
|
VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(5) |
|
VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VEC(6) |
|
+ /* Save begining of dst. */ |
|
+ movq %rdi, %rcx |
|
+ /* Align dst to VEC_SIZE - 1. */ |
|
+ orq $(VEC_SIZE - 1), %rdi |
|
VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %VEC(7) |
|
VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %VEC(8) |
|
- /* Save start and stop of the destination buffer. */ |
|
- movq %rdi, %r11 |
|
- leaq -VEC_SIZE(%rdi, %rdx), %rcx |
|
- /* Align destination for aligned stores in the loop. Compute |
|
- how much destination is misaligned. */ |
|
- movq %rdi, %r8 |
|
- andq $(VEC_SIZE - 1), %r8 |
|
- /* Get the negative of offset for alignment. */ |
|
- subq $VEC_SIZE, %r8 |
|
- /* Adjust source. */ |
|
- subq %r8, %rsi |
|
- /* Adjust destination which should be aligned now. */ |
|
- subq %r8, %rdi |
|
- /* Adjust length. */ |
|
- addq %r8, %rdx |
|
|
|
- .p2align 4 |
|
+ /* Subtract dst from src. Add back after dst aligned. */ |
|
+ subq %rcx, %rsi |
|
+ /* Finish aligning dst. */ |
|
+ incq %rdi |
|
+ /* Restore src adjusted with new value for aligned dst. */ |
|
+ addq %rdi, %rsi |
|
+ /* Store end of buffer minus tail in rdx. */ |
|
+ leaq (VEC_SIZE * -4)(%rcx, %rdx), %rdx |
|
+ |
|
+ /* Dont use multi-byte nop to align. */ |
|
+ .p2align 4,, 11 |
|
L(loop_4x_vec_forward): |
|
/* Copy 4 * VEC a time forward. */ |
|
- VMOVU (%rsi), %VEC(0) |
|
- VMOVU VEC_SIZE(%rsi), %VEC(1) |
|
- VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2) |
|
- VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3) |
|
+ VMOVU (%rsi), %VEC(1) |
|
+ VMOVU VEC_SIZE(%rsi), %VEC(2) |
|
+ VMOVU (VEC_SIZE * 2)(%rsi), %VEC(3) |
|
+ VMOVU (VEC_SIZE * 3)(%rsi), %VEC(4) |
|
subq $-(VEC_SIZE * 4), %rsi |
|
- addq $-(VEC_SIZE * 4), %rdx |
|
- VMOVA %VEC(0), (%rdi) |
|
- VMOVA %VEC(1), VEC_SIZE(%rdi) |
|
- VMOVA %VEC(2), (VEC_SIZE * 2)(%rdi) |
|
- VMOVA %VEC(3), (VEC_SIZE * 3)(%rdi) |
|
+ VMOVA %VEC(1), (%rdi) |
|
+ VMOVA %VEC(2), VEC_SIZE(%rdi) |
|
+ VMOVA %VEC(3), (VEC_SIZE * 2)(%rdi) |
|
+ VMOVA %VEC(4), (VEC_SIZE * 3)(%rdi) |
|
subq $-(VEC_SIZE * 4), %rdi |
|
- cmpq $(VEC_SIZE * 4), %rdx |
|
+ cmpq %rdi, %rdx |
|
ja L(loop_4x_vec_forward) |
|
/* Store the last 4 * VEC. */ |
|
- VMOVU %VEC(5), (%rcx) |
|
- VMOVU %VEC(6), -VEC_SIZE(%rcx) |
|
- VMOVU %VEC(7), -(VEC_SIZE * 2)(%rcx) |
|
- VMOVU %VEC(8), -(VEC_SIZE * 3)(%rcx) |
|
+ VMOVU %VEC(5), (VEC_SIZE * 3)(%rdx) |
|
+ VMOVU %VEC(6), (VEC_SIZE * 2)(%rdx) |
|
+ VMOVU %VEC(7), VEC_SIZE(%rdx) |
|
+ VMOVU %VEC(8), (%rdx) |
|
/* Store the first VEC. */ |
|
- VMOVU %VEC(4), (%r11) |
|
+ VMOVU %VEC(0), (%rcx) |
|
+ /* Keep L(nop_backward) target close to jmp for 2-byte encoding. |
|
+ */ |
|
+L(nop_backward): |
|
VZEROUPPER_RETURN |
|
|
|
+ .p2align 4,, 8 |
|
+L(more_8x_vec_backward_check_nop): |
|
+ /* rcx contains dst - src. Test for dst == src to skip all of |
|
+ memmove. */ |
|
+ testq %rcx, %rcx |
|
+ jz L(nop_backward) |
|
L(more_8x_vec_backward): |
|
/* Load the first 4 * VEC and last VEC to support overlapping |
|
addresses. */ |
|
- VMOVU (%rsi), %VEC(4) |
|
+ |
|
+ /* First vec was also loaded into VEC(0). */ |
|
VMOVU VEC_SIZE(%rsi), %VEC(5) |
|
VMOVU (VEC_SIZE * 2)(%rsi), %VEC(6) |
|
+ /* Begining of region for 4x backward copy stored in rcx. */ |
|
+ leaq (VEC_SIZE * -4 + -1)(%rdi, %rdx), %rcx |
|
VMOVU (VEC_SIZE * 3)(%rsi), %VEC(7) |
|
- VMOVU -VEC_SIZE(%rsi,%rdx), %VEC(8) |
|
- /* Save stop of the destination buffer. */ |
|
- leaq -VEC_SIZE(%rdi, %rdx), %r11 |
|
- /* Align destination end for aligned stores in the loop. Compute |
|
- how much destination end is misaligned. */ |
|
- leaq -VEC_SIZE(%rsi, %rdx), %rcx |
|
- movq %r11, %r9 |
|
- movq %r11, %r8 |
|
- andq $(VEC_SIZE - 1), %r8 |
|
- /* Adjust source. */ |
|
- subq %r8, %rcx |
|
- /* Adjust the end of destination which should be aligned now. */ |
|
- subq %r8, %r9 |
|
- /* Adjust length. */ |
|
- subq %r8, %rdx |
|
- |
|
- .p2align 4 |
|
+ VMOVU -VEC_SIZE(%rsi, %rdx), %VEC(8) |
|
+ /* Subtract dst from src. Add back after dst aligned. */ |
|
+ subq %rdi, %rsi |
|
+ /* Align dst. */ |
|
+ andq $-(VEC_SIZE), %rcx |
|
+ /* Restore src. */ |
|
+ addq %rcx, %rsi |
|
+ |
|
+ /* Don't use multi-byte nop to align. */ |
|
+ .p2align 4,, 11 |
|
L(loop_4x_vec_backward): |
|
/* Copy 4 * VEC a time backward. */ |
|
- VMOVU (%rcx), %VEC(0) |
|
- VMOVU -VEC_SIZE(%rcx), %VEC(1) |
|
- VMOVU -(VEC_SIZE * 2)(%rcx), %VEC(2) |
|
- VMOVU -(VEC_SIZE * 3)(%rcx), %VEC(3) |
|
- addq $-(VEC_SIZE * 4), %rcx |
|
- addq $-(VEC_SIZE * 4), %rdx |
|
- VMOVA %VEC(0), (%r9) |
|
- VMOVA %VEC(1), -VEC_SIZE(%r9) |
|
- VMOVA %VEC(2), -(VEC_SIZE * 2)(%r9) |
|
- VMOVA %VEC(3), -(VEC_SIZE * 3)(%r9) |
|
- addq $-(VEC_SIZE * 4), %r9 |
|
- cmpq $(VEC_SIZE * 4), %rdx |
|
- ja L(loop_4x_vec_backward) |
|
+ VMOVU (VEC_SIZE * 3)(%rsi), %VEC(1) |
|
+ VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2) |
|
+ VMOVU (VEC_SIZE * 1)(%rsi), %VEC(3) |
|
+ VMOVU (VEC_SIZE * 0)(%rsi), %VEC(4) |
|
+ addq $(VEC_SIZE * -4), %rsi |
|
+ VMOVA %VEC(1), (VEC_SIZE * 3)(%rcx) |
|
+ VMOVA %VEC(2), (VEC_SIZE * 2)(%rcx) |
|
+ VMOVA %VEC(3), (VEC_SIZE * 1)(%rcx) |
|
+ VMOVA %VEC(4), (VEC_SIZE * 0)(%rcx) |
|
+ addq $(VEC_SIZE * -4), %rcx |
|
+ cmpq %rcx, %rdi |
|
+ jb L(loop_4x_vec_backward) |
|
/* Store the first 4 * VEC. */ |
|
- VMOVU %VEC(4), (%rdi) |
|
+ VMOVU %VEC(0), (%rdi) |
|
VMOVU %VEC(5), VEC_SIZE(%rdi) |
|
VMOVU %VEC(6), (VEC_SIZE * 2)(%rdi) |
|
VMOVU %VEC(7), (VEC_SIZE * 3)(%rdi) |
|
/* Store the last VEC. */ |
|
- VMOVU %VEC(8), (%r11) |
|
+ VMOVU %VEC(8), -VEC_SIZE(%rdx, %rdi) |
|
+ VZEROUPPER_RETURN |
|
+ |
|
+#if defined USE_MULTIARCH && IS_IN (libc) |
|
+ /* L(skip_short_movsb_check) is only used with ERMS. Not for |
|
+ FSRM. */ |
|
+ .p2align 5,, 16 |
|
+# if ALIGN_MOVSB |
|
+L(skip_short_movsb_check): |
|
+# if MOVSB_ALIGN_TO > VEC_SIZE |
|
+ VMOVU VEC_SIZE(%rsi), %VEC(1) |
|
+# endif |
|
+# if MOVSB_ALIGN_TO > (VEC_SIZE * 2) |
|
+# error Unsupported MOVSB_ALIGN_TO |
|
+# endif |
|
+ /* If CPU does not have FSRM two options for aligning. Align src |
|
+ if dst and src 4k alias. Otherwise align dst. */ |
|
+ testl $(PAGE_SIZE - 512), %ecx |
|
+ jnz L(movsb_align_dst) |
|
+ /* Fall through. dst and src 4k alias. It's better to align src |
|
+ here because the bottleneck will be loads dues to the false |
|
+ dependency on dst. */ |
|
+ |
|
+ /* rcx already has dst - src. */ |
|
+ movq %rcx, %r9 |
|
+ /* Add src to len. Subtract back after src aligned. -1 because |
|
+ src is initially aligned to MOVSB_ALIGN_TO - 1. */ |
|
+ leaq -1(%rsi, %rdx), %rcx |
|
+ /* Inclusively align src to MOVSB_ALIGN_TO - 1. */ |
|
+ orq $(MOVSB_ALIGN_TO - 1), %rsi |
|
+ /* Restore dst and len adjusted with new values for aligned dst. |
|
+ */ |
|
+ leaq 1(%rsi, %r9), %rdi |
|
+ subq %rsi, %rcx |
|
+ /* Finish aligning src. */ |
|
+ incq %rsi |
|
+ |
|
+ rep movsb |
|
+ |
|
+ VMOVU %VEC(0), (%r8) |
|
+# if MOVSB_ALIGN_TO > VEC_SIZE |
|
+ VMOVU %VEC(1), VEC_SIZE(%r8) |
|
+# endif |
|
VZEROUPPER_RETURN |
|
+# endif |
|
+ |
|
+ .p2align 4,, 12 |
|
+L(movsb): |
|
+ movq %rdi, %rcx |
|
+ subq %rsi, %rcx |
|
+ /* Go to backwards temporal copy if overlap no matter what as |
|
+ backward REP MOVSB is slow and we don't want to use NT stores if |
|
+ there is overlap. */ |
|
+ cmpq %rdx, %rcx |
|
+ /* L(more_8x_vec_backward_check_nop) checks for src == dst. */ |
|
+ jb L(more_8x_vec_backward_check_nop) |
|
+# if ALIGN_MOVSB |
|
+ /* Save dest for storing aligning VECs later. */ |
|
+ movq %rdi, %r8 |
|
+# endif |
|
+ /* If above __x86_rep_movsb_stop_threshold most likely is |
|
+ candidate for NT moves aswell. */ |
|
+ cmp __x86_rep_movsb_stop_threshold(%rip), %RDX_LP |
|
+ jae L(large_memcpy_2x_check) |
|
+# if AVOID_SHORT_DISTANCE_REP_MOVSB || ALIGN_MOVSB |
|
+ /* Only avoid short movsb if CPU has FSRM. */ |
|
+ testl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, __x86_string_control(%rip) |
|
+ jz L(skip_short_movsb_check) |
|
+# if AVOID_SHORT_DISTANCE_REP_MOVSB |
|
+ /* Avoid "rep movsb" if RCX, the distance between source and |
|
+ destination, is N*4GB + [1..63] with N >= 0. */ |
|
+ |
|
+ /* ecx contains dst - src. Early check for backward copy |
|
+ conditions means only case of slow movsb with src = dst + [0, |
|
+ 63] is ecx in [-63, 0]. Use unsigned comparison with -64 check |
|
+ for that case. */ |
|
+ cmpl $-64, %ecx |
|
+ ja L(more_8x_vec_forward) |
|
+# endif |
|
+# endif |
|
+# if ALIGN_MOVSB |
|
+# if MOVSB_ALIGN_TO > VEC_SIZE |
|
+ VMOVU VEC_SIZE(%rsi), %VEC(1) |
|
+# endif |
|
+# if MOVSB_ALIGN_TO > (VEC_SIZE * 2) |
|
+# error Unsupported MOVSB_ALIGN_TO |
|
+# endif |
|
+ /* Fall through means cpu has FSRM. In that case exclusively |
|
+ align destination. */ |
|
+L(movsb_align_dst): |
|
+ /* Subtract dst from src. Add back after dst aligned. */ |
|
+ subq %rdi, %rsi |
|
+ /* Exclusively align dst to MOVSB_ALIGN_TO (64). */ |
|
+ addq $(MOVSB_ALIGN_TO - 1), %rdi |
|
+ /* Add dst to len. Subtract back after dst aligned. */ |
|
+ leaq (%r8, %rdx), %rcx |
|
+ /* Finish aligning dst. */ |
|
+ andq $-(MOVSB_ALIGN_TO), %rdi |
|
+ /* Restore src and len adjusted with new values for aligned dst. |
|
+ */ |
|
+ addq %rdi, %rsi |
|
+ subq %rdi, %rcx |
|
+ |
|
+ rep movsb |
|
+ |
|
+ /* Store VECs loaded for aligning. */ |
|
+ VMOVU %VEC(0), (%r8) |
|
+# if MOVSB_ALIGN_TO > VEC_SIZE |
|
+ VMOVU %VEC(1), VEC_SIZE(%r8) |
|
+# endif |
|
+ VZEROUPPER_RETURN |
|
+# else /* !ALIGN_MOVSB. */ |
|
+L(skip_short_movsb_check): |
|
+ mov %RDX_LP, %RCX_LP |
|
+ rep movsb |
|
+ ret |
|
+# endif |
|
+#endif |
|
|
|
+ .p2align 4,, 10 |
|
#if (defined USE_MULTIARCH || VEC_SIZE == 16) && IS_IN (libc) |
|
- .p2align 4 |
|
+L(large_memcpy_2x_check): |
|
+ cmp __x86_rep_movsb_threshold(%rip), %RDX_LP |
|
+ jb L(more_8x_vec_check) |
|
L(large_memcpy_2x): |
|
- /* Compute absolute value of difference between source and |
|
- destination. */ |
|
- movq %rdi, %r9 |
|
- subq %rsi, %r9 |
|
- movq %r9, %r8 |
|
- leaq -1(%r9), %rcx |
|
- sarq $63, %r8 |
|
- xorq %r8, %r9 |
|
- subq %r8, %r9 |
|
- /* Don't use non-temporal store if there is overlap between |
|
- destination and source since destination may be in cache when |
|
- source is loaded. */ |
|
- cmpq %r9, %rdx |
|
- ja L(more_8x_vec_check) |
|
+ /* To reach this point it is impossible for dst > src and |
|
+ overlap. Remaining to check is src > dst and overlap. rcx |
|
+ already contains dst - src. Negate rcx to get src - dst. If |
|
+ length > rcx then there is overlap and forward copy is best. */ |
|
+ negq %rcx |
|
+ cmpq %rcx, %rdx |
|
+ ja L(more_8x_vec_forward) |
|
|
|
/* Cache align destination. First store the first 64 bytes then |
|
adjust alignments. */ |
|
- VMOVU (%rsi), %VEC(8) |
|
-#if VEC_SIZE < 64 |
|
- VMOVU VEC_SIZE(%rsi), %VEC(9) |
|
-#if VEC_SIZE < 32 |
|
- VMOVU (VEC_SIZE * 2)(%rsi), %VEC(10) |
|
- VMOVU (VEC_SIZE * 3)(%rsi), %VEC(11) |
|
-#endif |
|
-#endif |
|
- VMOVU %VEC(8), (%rdi) |
|
-#if VEC_SIZE < 64 |
|
- VMOVU %VEC(9), VEC_SIZE(%rdi) |
|
-#if VEC_SIZE < 32 |
|
- VMOVU %VEC(10), (VEC_SIZE * 2)(%rdi) |
|
- VMOVU %VEC(11), (VEC_SIZE * 3)(%rdi) |
|
-#endif |
|
-#endif |
|
+ |
|
+ /* First vec was also loaded into VEC(0). */ |
|
+# if VEC_SIZE < 64 |
|
+ VMOVU VEC_SIZE(%rsi), %VEC(1) |
|
+# if VEC_SIZE < 32 |
|
+ VMOVU (VEC_SIZE * 2)(%rsi), %VEC(2) |
|
+ VMOVU (VEC_SIZE * 3)(%rsi), %VEC(3) |
|
+# endif |
|
+# endif |
|
+ VMOVU %VEC(0), (%rdi) |
|
+# if VEC_SIZE < 64 |
|
+ VMOVU %VEC(1), VEC_SIZE(%rdi) |
|
+# if VEC_SIZE < 32 |
|
+ VMOVU %VEC(2), (VEC_SIZE * 2)(%rdi) |
|
+ VMOVU %VEC(3), (VEC_SIZE * 3)(%rdi) |
|
+# endif |
|
+# endif |
|
+ |
|
/* Adjust source, destination, and size. */ |
|
movq %rdi, %r8 |
|
andq $63, %r8 |
|
@@ -614,9 +767,13 @@ L(large_memcpy_2x): |
|
/* Adjust length. */ |
|
addq %r8, %rdx |
|
|
|
- /* Test if source and destination addresses will alias. If they do |
|
- the larger pipeline in large_memcpy_4x alleviated the |
|
+ /* Test if source and destination addresses will alias. If they |
|
+ do the larger pipeline in large_memcpy_4x alleviated the |
|
performance drop. */ |
|
+ |
|
+ /* ecx contains -(dst - src). not ecx will return dst - src - 1 |
|
+ which works for testing aliasing. */ |
|
+ notl %ecx |
|
testl $(PAGE_SIZE - VEC_SIZE * 8), %ecx |
|
jz L(large_memcpy_4x) |
|
|
|
@@ -704,8 +861,8 @@ L(loop_large_memcpy_4x_outer): |
|
/* ecx stores inner loop counter. */ |
|
movl $(PAGE_SIZE / LARGE_LOAD_SIZE), %ecx |
|
L(loop_large_memcpy_4x_inner): |
|
- /* Only one prefetch set per page as doing 4 pages give more time |
|
- for prefetcher to keep up. */ |
|
+ /* Only one prefetch set per page as doing 4 pages give more |
|
+ time for prefetcher to keep up. */ |
|
PREFETCH_ONE_SET(1, (%rsi), PREFETCHED_LOAD_SIZE) |
|
PREFETCH_ONE_SET(1, (%rsi), PAGE_SIZE + PREFETCHED_LOAD_SIZE) |
|
PREFETCH_ONE_SET(1, (%rsi), PAGE_SIZE * 2 + PREFETCHED_LOAD_SIZE)
|
|
|