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90 lines
3.6 KiB
90 lines
3.6 KiB
2 weeks ago
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Keith Seitz <keiths@redhat.com>
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Date: Thu, 6 May 2021 14:12:00 -0400
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Subject: gdb-rhbz1870031-p10-prefixed-insn-1of3.patch
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;; Backport "displaced stepping across addpcis/lnia"
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;; (Will Schmidt, RHBZ 1870031)
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commit e3d528d7e6a6b863d30aaecf74adf8c78286f84c
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Author: Will Schmidt <will_schmidt@vnet.ibm.com>
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Date: Mon Apr 12 13:35:54 2021 -0500
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[PATCH, rs6000, v3][PR gdb/27525] displaced stepping across addpcis/lnia.
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This addresses PR gdb/27525. The lnia and other variations
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of the addpcis instruction write the value of the NIA into a target register.
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If we are single-stepping across a breakpoint, the instruction is executed
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from a displaced location, and thusly the written value of the PC/NIA
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will be incorrect. The changes here will measure the displacement
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offset, and adjust the target register value to compensate.
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YYYY-MM-DD Will Schmidt <will_schmidt@vnet.ibm.com>
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gdb/ChangeLog:
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* rs6000-tdep.c (ppc_displaced_step_fixup): Update to handle
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the addpcis/lnia instruction.
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gdb/testsuite/ChangeLog:
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* gdb.arch/powerpc-addpcis.exp: Testcase harness to
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exercise single-stepping over subpcis,lnia,addpcis instructions
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with displacement.
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* gdb.arch/powerpc-addpcis.s: Testcase with stream
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of addpcis/lnia/subpcis instructions.
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* gdb.arch/powerpc-lnia.exp: Testcase harness to exercise
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single-stepping over lnia instructions with displacement.
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* gdb.arch/powerpc-lnia.s: Testcase with stream of
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lnia instructions.
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diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
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--- a/gdb/rs6000-tdep.c
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+++ b/gdb/rs6000-tdep.c
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@@ -836,6 +836,12 @@ typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
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#define STHCX_INSTRUCTION 0x7c0005ad
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#define STQCX_INSTRUCTION 0x7c00016d
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+/* Instruction masks for single-stepping of addpcis/lnia. */
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+#define ADDPCIS_INSN 0x4c000004
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+#define ADDPCIS_INSN_MASK 0xfc00003e
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+#define ADDPCIS_TARGET_REGISTER 0x03F00000
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+#define ADDPCIS_INSN_REGSHIFT 21
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+
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/* Check if insn is one of the Load And Reserve instructions used for atomic
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sequences. */
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#define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
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@@ -923,8 +929,31 @@ ppc_displaced_step_fixup (struct gdbarch *gdbarch,
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paddress (gdbarch, from), paddress (gdbarch, to));
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+ /* Handle the addpcis/lnia instruction. */
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+ if ((insn & ADDPCIS_INSN_MASK) == ADDPCIS_INSN)
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+ {
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+ LONGEST displaced_offset;
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+ ULONGEST current_val;
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+ /* Measure the displacement. */
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+ displaced_offset = from - to;
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+ /* Identify the target register that was updated by the instruction. */
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+ int regnum = (insn & ADDPCIS_TARGET_REGISTER) >> ADDPCIS_INSN_REGSHIFT;
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+ /* Read and update the target value. */
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+ regcache_cooked_read_unsigned (regs, regnum , ¤t_val);
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+ if (debug_displaced)
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+ fprintf_unfiltered (gdb_stdlog,
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+ "displaced: {ppc} addpcis target regnum %d was "
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+ "0x%lx now 0x%lx",
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+ regnum, current_val,
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+ current_val + displaced_offset);
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+ regcache_cooked_write_unsigned (regs, regnum,
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+ current_val + displaced_offset);
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+ /* point the PC back at the non-displaced instruction. */
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+ regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
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+ from + offset);
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+ }
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/* Handle PC-relative branch instructions. */
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- if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
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+ else if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
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{
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ULONGEST current_pc;
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