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68 lines
2.5 KiB
68 lines
2.5 KiB
From 7164abebecfbf450cdc55133eb3162f8c1501ff3 Mon Sep 17 00:00:00 2001 |
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From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com> |
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Date: Tue, 19 Jun 2018 16:45:21 -0700 |
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Subject: [PATCH libdrm] intel: Introducing Amber Lake platform |
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MIME-Version: 1.0 |
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Content-Type: text/plain; charset=UTF-8 |
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Content-Transfer-Encoding: 8bit |
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Amber Lake uses the same gen graphics as Kaby Lake, including a id |
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that were previously marked as reserved on Kaby Lake, but that now is |
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moved to AML page. |
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So, let's just move it to AML macro that will feed into KBL macro |
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just to keep it better organized to make easier future code review |
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but it will be handled as a KBL. |
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This is a copy of merged i915's |
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commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") |
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: José Roberto de Souza <jose.souza@intel.com> |
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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--- |
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intel/intel_chipset.h | 9 ++++++--- |
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1 file changed, 6 insertions(+), 3 deletions(-) |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index 44e65f9e..583d6447 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -201,7 +201,6 @@ |
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#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 |
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#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E |
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#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E |
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-#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C |
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#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 |
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#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 |
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#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 |
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@@ -213,6 +212,9 @@ |
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#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A |
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#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D |
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+#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C |
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+#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 |
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+ |
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#define PCI_CHIP_BROXTON_0 0x0A84 |
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#define PCI_CHIP_BROXTON_1 0x1A84 |
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#define PCI_CHIP_BROXTON_2 0x5A84 |
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@@ -468,12 +470,13 @@ |
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#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ |
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- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ |
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(devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ |
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(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ |
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- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) |
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+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ |
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+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ |
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+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) |
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#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ |
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ |
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-- |
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2.17.1 |
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