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85 lines
3.9 KiB
85 lines
3.9 KiB
From 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 Mon Sep 17 00:00:00 2001 |
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From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com> |
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Date: Tue, 19 Jun 2018 16:45:20 -0700 |
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Subject: [PATCH libdrm] intel: Introducing Whiskey Lake platform |
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MIME-Version: 1.0 |
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Content-Type: text/plain; charset=UTF-8 |
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Content-Transfer-Encoding: 8bit |
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Whiskey Lake uses the same gen graphics as Coffe Lake, including some |
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ids that were previously marked as reserved on Coffe Lake, but that |
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now are moved to WHL page. |
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So, let's just move them to WHL macros that will feed into CFL macro |
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just to keep it better organized to make easier future code review |
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but it will be handled as a CFL. |
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This is a copy of merged i915's |
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commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") |
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: José Roberto de Souza <jose.souza@intel.com> |
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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--- |
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intel/intel_chipset.h | 33 +++++++++++++++++---------------- |
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1 file changed, 17 insertions(+), 16 deletions(-) |
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h |
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index 32b2c48f..44e65f9e 100644 |
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--- a/intel/intel_chipset.h |
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+++ b/intel/intel_chipset.h |
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@@ -231,16 +231,17 @@ |
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#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A |
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#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B |
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#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 |
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-#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 |
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-#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 |
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-#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 |
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-#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 |
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+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 |
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+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 |
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+ |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 |
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+#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 |
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#define PCI_CHIP_CANNONLAKE_0 0x5A51 |
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#define PCI_CHIP_CANNONLAKE_1 0x5A59 |
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@@ -510,16 +511,16 @@ |
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#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) |
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-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ |
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+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ |
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ |
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ |
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+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) |
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#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ |
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IS_CFL_H(devid) || \ |
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-- |
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2.17.1 |
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