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mesa package update 

Signed-off-by: guibuilder_pel7x64builder0 <guibuilder@powerel.org>
master
guibuilder_pel7x64builder0 7 years ago
parent
5fd75af377
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6037f90dbf
18 changed files with 5466 additions and 0 deletions
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  1. 45
      SOURCES/0001-intel-Add-more-Coffee-Lake-PCI-IDs.patch
  2. 33
      SOURCES/0001-intel-blorp-Use-mocs.tex-for-depth-stencil.patch
  3. 2492
      SOURCES/0001-mesa-Squash-merge-of-S3TC-support.patch
  4. 182
      SOURCES/0002-anv-blorp-Add-a-device-parameter-to-blorp_surf_for_a.patch
  5. 312
      SOURCES/0003-blorp-Turn-anv_CmdCopyBuffer-into-a-blorp_buffer_cop.patch
  6. 288
      SOURCES/0004-intel-blorp-Make-the-MOCS-setting-part-of-blorp_addr.patch
  7. 136
      SOURCES/0005-i965-Use-PTE-MOCS-for-all-external-buffers.patch
  8. 117
      SOURCES/Mesa-MLAA-License-Clarification-Email.txt
  9. 28
      SOURCES/make-git-snapshot.sh
  10. 5
      SOURCES/make-release-tarball.sh
  11. 328
      SOURCES/mesa-10.2-evergreen-big-endian.patch
  12. 194
      SOURCES/mesa-17.3-final.patch
  13. 156
      SOURCES/mesa-8.0-llvmpipe-shmget.patch
  14. 13
      SOURCES/mesa-8.0.1-fix-16bpp.patch
  15. 36
      SOURCES/mesa-9.2-hardware-float.patch
  16. 12
      SOURCES/nv50-fix-build.patch
  17. 55
      SOURCES/sanitize-tarball.sh
  18. 1034
      SPECS/mesa.spec

45
SOURCES/0001-intel-Add-more-Coffee-Lake-PCI-IDs.patch
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@ -0,0 +1,45 @@ @@ -0,0 +1,45 @@
From fe668b5c155aee4443dde0748065241e09293302 Mon Sep 17 00:00:00 2001
From: Anuj Phogat <anuj.phogat@gmail.com>
Date: Fri, 5 Jan 2018 09:17:36 -0800
Subject: [PATCH] intel: Add more Coffee Lake PCI IDs

More Coffee Lake PCI IDs have been added to the spec.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/pci_ids/i965_pci_ids.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 0dd01a4..9616f7d 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -167,15 +167,23 @@ CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9A, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA0, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA3, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA9, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA2, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
-CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
--
2.9.5

33
SOURCES/0001-intel-blorp-Use-mocs.tex-for-depth-stencil.patch
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@ -0,0 +1,33 @@ @@ -0,0 +1,33 @@
From d284bd93e387019b34796b6d8e7a985d60590157 Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 14:31:51 -0700
Subject: [PATCH 1/5] intel/blorp: Use mocs.tex for depth stencil

Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lyude <lyude@redhat.com>
---
src/intel/blorp/blorp_genX_exec.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 93534169ef..565acca929 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1364,11 +1364,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
return;
struct isl_depth_stencil_hiz_emit_info info = {
-#if GEN_GEN >= 7
- .mocs = 1, /* GEN7_MOCS_L3 */
-#else
- .mocs = 0,
-#endif
+ .mocs = batch->blorp->mocs.tex,
};
if (params->depth.enabled) {
--
2.14.3

2492
SOURCES/0001-mesa-Squash-merge-of-S3TC-support.patch
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File diff suppressed because it is too large Load Diff

182
SOURCES/0002-anv-blorp-Add-a-device-parameter-to-blorp_surf_for_a.patch
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@ -0,0 +1,182 @@ @@ -0,0 +1,182 @@
From ee170635c5be54cf644ef5c8d4574f30764e244f Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 15:18:45 -0700
Subject: [PATCH 2/5] anv/blorp: Add a device parameter to
blorp_surf_for_anv_image

Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lyude <lyude@redhat.com>
---
src/intel/vulkan/anv_blorp.c | 54 ++++++++++++++++++++++++++++----------------
1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 79f5234c55..c00d38b52c 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -176,7 +176,8 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
}
static void
-get_blorp_surf_for_anv_image(const struct anv_image *image,
+get_blorp_surf_for_anv_image(const struct anv_device *device,
+ const struct anv_image *image,
VkImageAspectFlags aspect,
enum isl_aux_usage aux_usage,
struct blorp_surf *blorp_surf)
@@ -257,9 +258,11 @@ void anv_CmdCopyImage(
VkImageAspectFlagBits aspect = (1 << a);
struct blorp_surf src_surf, dst_surf;
- get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ src_image, aspect, src_image->aux_usage,
&src_surf);
- get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ dst_image, aspect, dst_image->aux_usage,
&dst_surf);
for (unsigned i = 0; i < layer_count; i++) {
@@ -308,8 +311,8 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
for (unsigned r = 0; r < regionCount; r++) {
const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
- get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
- &image.surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
+ anv_image->aux_usage, &image.surf);
image.offset =
anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
image.level = pRegions[r].imageSubresource.mipLevel;
@@ -454,9 +457,11 @@ void anv_CmdBlitImage(
const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
- get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ src_image, src_res->aspectMask,
src_image->aux_usage, &src);
- get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ dst_image, dst_res->aspectMask,
dst_image->aux_usage, &dst);
struct anv_format src_format =
@@ -832,7 +837,8 @@ void anv_CmdClearColorImage(
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_COLOR_BIT,
image->aux_usage, &surf);
for (unsigned r = 0; r < rangeCount; r++) {
@@ -885,14 +891,16 @@ void anv_CmdClearDepthStencilImage(
struct blorp_surf depth, stencil;
if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_DEPTH_BIT,
ISL_AUX_USAGE_NONE, &depth);
} else {
memset(&depth, 0, sizeof(depth));
}
if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_STENCIL_BIT,
ISL_AUX_USAGE_NONE, &stencil);
} else {
memset(&stencil, 0, sizeof(stencil));
@@ -1212,7 +1220,8 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
struct anv_image_view *iview = fb->attachments[a];
const struct anv_image *image = iview->image;
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
att_state->aux_usage, &surf);
if (att_state->fast_clear) {
@@ -1359,7 +1368,8 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
}
static void
-resolve_image(struct blorp_batch *batch,
+resolve_image(struct anv_device *device,
+ struct blorp_batch *batch,
const struct anv_image *src_image,
enum isl_aux_usage src_aux_usage,
uint32_t src_level, uint32_t src_layer,
@@ -1380,9 +1390,9 @@ resolve_image(struct blorp_batch *batch,
VkImageAspectFlagBits aspect = 1 << a;
struct blorp_surf src_surf, dst_surf;
- get_blorp_surf_for_anv_image(src_image, aspect,
+ get_blorp_surf_for_anv_image(device, src_image, aspect,
src_aux_usage, &src_surf);
- get_blorp_surf_for_anv_image(dst_image, aspect,
+ get_blorp_surf_for_anv_image(device, dst_image, aspect,
dst_aux_usage, &dst_surf);
blorp_blit(batch,
@@ -1422,7 +1432,7 @@ void anv_CmdResolveImage(
anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
for (uint32_t layer = 0; layer < layer_count; layer++) {
- resolve_image(&batch,
+ resolve_image(cmd_buffer->device, &batch,
src_image, src_image->aux_usage,
pRegions[r].srcSubresource.mipLevel,
pRegions[r].srcSubresource.baseArrayLayer + layer,
@@ -1456,7 +1466,8 @@ anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
image->aux_usage == ISL_AUX_USAGE_NONE ?
ISL_AUX_USAGE_CCS_D : image->aux_usage,
&surf);
@@ -1553,7 +1564,8 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
assert(src_iview->aspect_mask == dst_iview->aspect_mask);
- resolve_image(&batch, src_iview->image, src_aux_usage,
+ resolve_image(cmd_buffer->device, &batch,
+ src_iview->image, src_aux_usage,
src_iview->isl.base_level,
src_iview->isl.base_array_layer,
dst_iview->image, dst_aux_usage,
@@ -1590,8 +1602,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
- ISL_AUX_USAGE_NONE, &surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image,
+ VK_IMAGE_ASPECT_DEPTH_BIT, ISL_AUX_USAGE_NONE,
+ &surf);
/* Manually add the aux HiZ surf */
surf.aux_surf = &image->aux_surface.isl,
@@ -1634,7 +1647,8 @@ anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
BLORP_BATCH_PREDICATE_ENABLE);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
image->aux_usage == ISL_AUX_USAGE_CCS_E ?
ISL_AUX_USAGE_CCS_E : ISL_AUX_USAGE_CCS_D,
&surf);
--
2.14.3

312
SOURCES/0003-blorp-Turn-anv_CmdCopyBuffer-into-a-blorp_buffer_cop.patch
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@ -0,0 +1,312 @@ @@ -0,0 +1,312 @@
From d9266ae66c9db12a9c2578a33bbd5ebd131b489f Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon, 28 Aug 2017 15:57:20 -0700
Subject: [PATCH 3/5] blorp: Turn anv_CmdCopyBuffer into a blorp_buffer_copy()
helper.

I want to be able to copy between buffer objects using BLORP in the i965
driver. Anvil already had code to do this, in a reasonably efficient
manner - first using large bpp copies, then smaller bpp copies.

This patch moves that logic into BLORP as blorp_buffer_copy(), so we
can use it in both drivers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Lyude <lyude@redhat.com>
---
src/intel/blorp/blorp.h | 6 +++
src/intel/blorp/blorp_blit.c | 119 +++++++++++++++++++++++++++++++++++++++++++
src/intel/vulkan/anv_blorp.c | 117 +++++++-----------------------------------
3 files changed, 143 insertions(+), 99 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index d19920e87f..e712b4fbb3 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -133,6 +133,12 @@ blorp_copy(struct blorp_batch *batch,
uint32_t dst_x, uint32_t dst_y,
uint32_t src_width, uint32_t src_height);
+void
+blorp_buffer_copy(struct blorp_batch *batch,
+ struct blorp_address src,
+ struct blorp_address dst,
+ uint64_t size);
+
void
blorp_fast_clear(struct blorp_batch *batch,
const struct blorp_surf *surf, enum isl_format format,
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 35008cbbb0..b012a0a0b3 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2513,3 +2513,122 @@ blorp_copy(struct blorp_batch *batch,
do_blorp_blit(batch, &params, &wm_prog_key, &coords);
}
+
+static enum isl_format
+isl_format_for_size(unsigned size_B)
+{
+ switch (size_B) {
+ case 1: return ISL_FORMAT_R8_UINT;
+ case 2: return ISL_FORMAT_R8G8_UINT;
+ case 4: return ISL_FORMAT_R8G8B8A8_UINT;
+ case 8: return ISL_FORMAT_R16G16B16A16_UINT;
+ case 16: return ISL_FORMAT_R32G32B32A32_UINT;
+ default:
+ unreachable("Not a power-of-two format size");
+ }
+}
+
+/**
+ * Returns the greatest common divisor of a and b that is a power of two.
+ */
+static uint64_t
+gcd_pow2_u64(uint64_t a, uint64_t b)
+{
+ assert(a > 0 || b > 0);
+
+ unsigned a_log2 = ffsll(a) - 1;
+ unsigned b_log2 = ffsll(b) - 1;
+
+ /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
+ * case, the MIN2() will take the other one. If both are 0 then we will
+ * hit the assert above.
+ */
+ return 1 << MIN2(a_log2, b_log2);
+}
+
+static void
+do_buffer_copy(struct blorp_batch *batch,
+ struct blorp_address *src,
+ struct blorp_address *dst,
+ int width, int height, int block_size)
+{
+ /* The actual format we pick doesn't matter as blorp will throw it away.
+ * The only thing that actually matters is the size.
+ */
+ enum isl_format format = isl_format_for_size(block_size);
+
+ UNUSED bool ok;
+ struct isl_surf surf;
+ ok = isl_surf_init(batch->blorp->isl_dev, &surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = format,
+ .width = width,
+ .height = height,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = 1,
+ .row_pitch = width * block_size,
+ .usage = ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_RENDER_TARGET_BIT,
+ .tiling_flags = ISL_TILING_LINEAR_BIT);
+ assert(ok);
+
+ struct blorp_surf src_blorp_surf = {
+ .surf = &surf,
+ .addr = *src,
+ };
+
+ struct blorp_surf dst_blorp_surf = {
+ .surf = &surf,
+ .addr = *dst,
+ };
+
+ blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
+ 0, 0, 0, 0, width, height);
+}
+
+/* This is maximum possible width/height our HW can handle */
+#define MAX_SURFACE_DIM (1ull << 14)
+
+void
+blorp_buffer_copy(struct blorp_batch *batch,
+ struct blorp_address src,
+ struct blorp_address dst,
+ uint64_t size)
+{
+ uint64_t copy_size = size;
+
+ /* First, we compute the biggest format that can be used with the
+ * given offsets and size.
+ */
+ int bs = 16;
+ bs = gcd_pow2_u64(bs, src.offset);
+ bs = gcd_pow2_u64(bs, dst.offset);
+ bs = gcd_pow2_u64(bs, size);
+
+ /* First, we make a bunch of max-sized copies */
+ uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
+ while (copy_size >= max_copy_size) {
+ do_buffer_copy(batch, &src, &dst, MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
+ copy_size -= max_copy_size;
+ src.offset += max_copy_size;
+ dst.offset += max_copy_size;
+ }
+
+ /* Now make a max-width copy */
+ uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
+ assert(height < MAX_SURFACE_DIM);
+ if (height != 0) {
+ uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
+ do_buffer_copy(batch, &src, &dst, MAX_SURFACE_DIM, height, bs);
+ copy_size -= rect_copy_size;
+ src.offset += rect_copy_size;
+ dst.offset += rect_copy_size;
+ }
+
+ /* Finally, make a small copy to finish it off */
+ if (copy_size != 0) {
+ do_buffer_copy(batch, &src, &dst, copy_size / bs, 1, bs);
+ }
+}
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index c00d38b52c..3a64b60178 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -546,56 +546,6 @@ isl_format_for_size(unsigned size_B)
}
}
-static void
-do_buffer_copy(struct blorp_batch *batch,
- struct anv_bo *src, uint64_t src_offset,
- struct anv_bo *dst, uint64_t dst_offset,
- int width, int height, int block_size)
-{
- struct anv_device *device = batch->blorp->driver_ctx;
-
- /* The actual format we pick doesn't matter as blorp will throw it away.
- * The only thing that actually matters is the size.
- */
- enum isl_format format = isl_format_for_size(block_size);
-
- UNUSED bool ok;
- struct isl_surf surf;
- ok = isl_surf_init(&device->isl_dev, &surf,
- .dim = ISL_SURF_DIM_2D,
- .format = format,
- .width = width,
- .height = height,
- .depth = 1,
- .levels = 1,
- .array_len = 1,
- .samples = 1,
- .row_pitch = width * block_size,
- .usage = ISL_SURF_USAGE_TEXTURE_BIT |
- ISL_SURF_USAGE_RENDER_TARGET_BIT,
- .tiling_flags = ISL_TILING_LINEAR_BIT);
- assert(ok);
-
- struct blorp_surf src_blorp_surf = {
- .surf = &surf,
- .addr = {
- .buffer = src,
- .offset = src_offset,
- },
- };
-
- struct blorp_surf dst_blorp_surf = {
- .surf = &surf,
- .addr = {
- .buffer = dst,
- .offset = dst_offset,
- },
- };
-
- blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
- 0, 0, 0, 0, width, height);
-}
-
/**
* Returns the greatest common divisor of a and b that is a power of two.
*/
@@ -632,48 +582,16 @@ void anv_CmdCopyBuffer(
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (unsigned r = 0; r < regionCount; r++) {
- uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
- uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
- uint64_t copy_size = pRegions[r].size;
-
- /* First, we compute the biggest format that can be used with the
- * given offsets and size.
- */
- int bs = 16;
- bs = gcd_pow2_u64(bs, src_offset);
- bs = gcd_pow2_u64(bs, dst_offset);
- bs = gcd_pow2_u64(bs, pRegions[r].size);
-
- /* First, we make a bunch of max-sized copies */
- uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
- while (copy_size >= max_copy_size) {
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
- copy_size -= max_copy_size;
- src_offset += max_copy_size;
- dst_offset += max_copy_size;
- }
-
- /* Now make a max-width copy */
- uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
- assert(height < MAX_SURFACE_DIM);
- if (height != 0) {
- uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- MAX_SURFACE_DIM, height, bs);
- copy_size -= rect_copy_size;
- src_offset += rect_copy_size;
- dst_offset += rect_copy_size;
- }
+ struct blorp_address src = {
+ .buffer = src_buffer->bo,
+ .offset = src_buffer->offset + pRegions[r].srcOffset,
+ };
+ struct blorp_address dst = {
+ .buffer = dst_buffer->bo,
+ .offset = dst_buffer->offset + pRegions[r].dstOffset,
+ };
- /* Finally, make a small copy to finish it off */
- if (copy_size != 0) {
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- copy_size / bs, 1, bs);
- }
+ blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
}
blorp_batch_finish(&batch);
@@ -715,15 +633,16 @@ void anv_CmdUpdateBuffer(
anv_state_flush(cmd_buffer->device, tmp_data);
- int bs = 16;
- bs = gcd_pow2_u64(bs, dstOffset);
- bs = gcd_pow2_u64(bs, copy_size);
+ struct blorp_address src = {
+ .buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
+ .offset = tmp_data.offset,
+ };
+ struct blorp_address dst = {
+ .buffer = dst_buffer->bo,
+ .offset = dst_buffer->offset + dstOffset,
+ };
- do_buffer_copy(&batch,
- &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
- tmp_data.offset,
- dst_buffer->bo, dst_buffer->offset + dstOffset,
- copy_size / bs, 1, bs);
+ blorp_buffer_copy(&batch, src, dst, copy_size);
dataSize -= copy_size;
dstOffset += copy_size;
--
2.14.3

288
SOURCES/0004-intel-blorp-Make-the-MOCS-setting-part-of-blorp_addr.patch
Unescape View File

@ -0,0 +1,288 @@ @@ -0,0 +1,288 @@
From f70d7f3f4600febac0a6d1f62e14230eace8a67b Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 15:20:08 -0700
Subject: [PATCH 4/5] intel/blorp: Make the MOCS setting part of blorp_address

This makes our MOCS settings significantly more flexible.

Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lyude <lyude@redhat.com>
---
src/intel/blorp/blorp.h | 7 +------
src/intel/blorp/blorp_genX_exec.h | 16 +++++++--------
src/intel/vulkan/anv_blorp.c | 11 +++++++---
src/intel/vulkan/genX_blorp_exec.c | 1 +
src/mesa/drivers/dri/i965/brw_blorp.c | 31 +++++++++++++++--------------
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10 ++++++++++
6 files changed, 43 insertions(+), 33 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index e712b4fbb3..ac45828a42 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -45,12 +45,6 @@ struct blorp_context {
const struct brw_compiler *compiler;
- struct {
- uint32_t tex;
- uint32_t rb;
- uint32_t vb;
- } mocs;
-
bool (*lookup_shader)(struct blorp_context *blorp,
const void *key, uint32_t key_size,
uint32_t *kernel_out, void *prog_data_out);
@@ -95,6 +89,7 @@ struct blorp_address {
uint32_t read_domains;
uint32_t write_domain;
uint32_t offset;
+ uint32_t mocs;
};
struct blorp_surf
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 565acca929..d0f0299d17 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -269,7 +269,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[0].VertexBufferIndex = 0;
vb[0].BufferPitch = 3 * sizeof(float);
#if GEN_GEN >= 6
- vb[0].VertexBufferMOCS = batch->blorp->mocs.vb;
+ vb[0].VertexBufferMOCS = vb[0].BufferStartingAddress.mocs;
#endif
#if GEN_GEN >= 7
vb[0].AddressModifyEnable = true;
@@ -290,7 +290,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[1].VertexBufferIndex = 1;
vb[1].BufferPitch = 0;
#if GEN_GEN >= 6
- vb[1].VertexBufferMOCS = batch->blorp->mocs.vb;
+ vb[1].VertexBufferMOCS = vb[1].BufferStartingAddress.mocs;
#endif
#if GEN_GEN >= 7
vb[1].AddressModifyEnable = true;
@@ -1235,13 +1235,11 @@ blorp_emit_surface_state(struct blorp_batch *batch,
write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
- const uint32_t mocs =
- is_render_target ? batch->blorp->mocs.rb : batch->blorp->mocs.tex;
-
isl_surf_fill_state(batch->blorp->isl_dev, state,
.surf = &surf, .view = &surface->view,
.aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
- .mocs = mocs, .clear_color = surface->clear_color,
+ .mocs = surface->addr.mocs,
+ .clear_color = surface->clear_color,
.write_disables = write_disable_mask);
blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
@@ -1363,14 +1361,14 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
if (dw == NULL)
return;
- struct isl_depth_stencil_hiz_emit_info info = {
- .mocs = batch->blorp->mocs.tex,
- };
+ struct isl_depth_stencil_hiz_emit_info info = { };
if (params->depth.enabled) {
info.view = &params->depth.view;
+ info.mocs = params->depth.addr.mocs;
} else if (params->stencil.enabled) {
info.view = &params->stencil.view;
+ info.mocs = params->stencil.addr.mocs;
}
if (params->depth.enabled) {
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 3a64b60178..b7e9524a24 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -92,9 +92,6 @@ anv_device_init_blorp(struct anv_device *device)
anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
blorp_init(&device->blorp, device, &device->isl_dev);
device->blorp.compiler = device->instance->physicalDevice.compiler;
- device->blorp.mocs.tex = device->default_mocs;
- device->blorp.mocs.rb = device->default_mocs;
- device->blorp.mocs.vb = device->default_mocs;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.gen) {
@@ -156,6 +153,7 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
.addr = {
.buffer = buffer->bo,
.offset = buffer->offset + offset,
+ .mocs = device->default_mocs,
},
};
@@ -194,6 +192,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
.addr = {
.buffer = image->bo,
.offset = image->offset + surface->offset,
+ .mocs = device->default_mocs,
},
};
@@ -202,6 +201,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
blorp_surf->aux_addr = (struct blorp_address) {
.buffer = image->bo,
.offset = image->offset + image->aux_surface.offset,
+ .mocs = device->default_mocs,
};
blorp_surf->aux_usage = aux_usage;
}
@@ -585,10 +585,12 @@ void anv_CmdCopyBuffer(
struct blorp_address src = {
.buffer = src_buffer->bo,
.offset = src_buffer->offset + pRegions[r].srcOffset,
+ .mocs = cmd_buffer->device->default_mocs,
};
struct blorp_address dst = {
.buffer = dst_buffer->bo,
.offset = dst_buffer->offset + pRegions[r].dstOffset,
+ .mocs = cmd_buffer->device->default_mocs,
};
blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
@@ -636,10 +638,12 @@ void anv_CmdUpdateBuffer(
struct blorp_address src = {
.buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = tmp_data.offset,
+ .mocs = cmd_buffer->device->default_mocs,
};
struct blorp_address dst = {
.buffer = dst_buffer->bo,
.offset = dst_buffer->offset + dstOffset,
+ .mocs = cmd_buffer->device->default_mocs,
};
blorp_buffer_copy(&batch, src, dst, copy_size);
@@ -1530,6 +1534,7 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
surf.aux_addr = (struct blorp_address) {
.buffer = image->bo,
.offset = image->offset + image->aux_surface.offset,
+ .mocs = cmd_buffer->device->default_mocs,
};
surf.aux_usage = ISL_AUX_USAGE_HIZ;
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index f041fc71b5..b4b05c7022 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -134,6 +134,7 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
*addr = (struct blorp_address) {
.buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = vb_state.offset,
+ .mocs = cmd_buffer->device->default_mocs,
};
return vb_state.map;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index eb08de438d..2b7d960f0c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -82,15 +82,9 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.exec = gen5_blorp_exec;
break;
case 6:
- brw->blorp.mocs.tex = 0;
- brw->blorp.mocs.rb = 0;
- brw->blorp.mocs.vb = 0;
brw->blorp.exec = gen6_blorp_exec;
break;
case 7:
- brw->blorp.mocs.tex = GEN7_MOCS_L3;
- brw->blorp.mocs.rb = GEN7_MOCS_L3;
- brw->blorp.mocs.vb = GEN7_MOCS_L3;
if (brw->is_haswell) {
brw->blorp.exec = gen75_blorp_exec;
} else {
@@ -98,21 +92,12 @@ brw_blorp_init(struct brw_context *brw)
}
break;
case 8:
- brw->blorp.mocs.tex = BDW_MOCS_WB;
- brw->blorp.mocs.rb = BDW_MOCS_PTE;
- brw->blorp.mocs.vb = BDW_MOCS_WB;
brw->blorp.exec = gen8_blorp_exec;
break;
case 9:
- brw->blorp.mocs.tex = SKL_MOCS_WB;
- brw->blorp.mocs.rb = SKL_MOCS_PTE;
- brw->blorp.mocs.vb = SKL_MOCS_WB;
brw->blorp.exec = gen9_blorp_exec;
break;
case 10:
- brw->blorp.mocs.tex = CNL_MOCS_WB;
- brw->blorp.mocs.rb = CNL_MOCS_PTE;
- brw->blorp.mocs.vb = CNL_MOCS_WB;
brw->blorp.exec = gen10_blorp_exec;
break;
default:
@@ -123,6 +108,20 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.upload_shader = brw_blorp_upload_shader;
}
+static uint32_t tex_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_WB,
+ [9] = SKL_MOCS_WB,
+ [10] = CNL_MOCS_WB,
+};
+
+static uint32_t rb_mocs[] = {
+ [7] = GEN7_MOCS_L3,
+ [8] = BDW_MOCS_PTE,
+ [9] = SKL_MOCS_PTE,
+ [10] = CNL_MOCS_PTE,
+};
+
static void
blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
@@ -155,6 +154,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .mocs = is_render_target ? rb_mocs[devinfo->gen] : tex_mocs[devinfo->gen],
};
surf->aux_usage = aux_usage;
@@ -184,6 +184,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .mocs = surf->addr.mocs,
};
if (mt->mcs_buf) {
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 62d5c4a792..74c1add281 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -145,6 +145,16 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
.read_domains = I915_GEM_DOMAIN_VERTEX,
.write_domain = 0,
.offset = offset,
+
+#if GEN_GEN == 10
+ .mocs = CNL_MOCS_WB,
+#elif GEN_GEN == 9
+ .mocs = SKL_MOCS_WB,
+#elif GEN_GEN == 8
+ .mocs = BDW_MOCS_WB,
+#elif GEN_GEN == 7
+ .mocs = GEN7_MOCS_L3,
+#endif
};
return data;
--
2.14.3

136
SOURCES/0005-i965-Use-PTE-MOCS-for-all-external-buffers.patch
Unescape View File

@ -0,0 +1,136 @@ @@ -0,0 +1,136 @@
From 066ea39ce113d8fe1992a6892f7094a6dfae6242 Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Fri, 3 Nov 2017 15:26:17 -0700
Subject: [PATCH 5/5] i965: Use PTE MOCS for all external buffers

We were already using PTE for all render targets in case one happened to
get scanned out. However, this still wasn't 100% correct because there
are still possibly cases where we may want to texture from an external
buffer even though we don't know the caching mode. This can happen, for
instance, on buffers imported from another GPU via prime.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Tested-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lyude <lyude@redhat.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 7 ++++---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 23 ++++++++++++++++-------
2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2b7d960f0c..48b3da7375 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -108,14 +108,14 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.upload_shader = brw_blorp_upload_shader;
}
-static uint32_t tex_mocs[] = {
+static uint32_t wb_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
[10] = CNL_MOCS_WB,
};
-static uint32_t rb_mocs[] = {
+static uint32_t pte_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
@@ -154,7 +154,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
- .mocs = is_render_target ? rb_mocs[devinfo->gen] : tex_mocs[devinfo->gen],
+ .mocs = (is_render_target || mt->bo->external) ? pte_mocs[devinfo->gen] :
+ wb_mocs[devinfo->gen],
};
surf->aux_usage = aux_usage;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 17e760c329..87f1aa379d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -60,20 +60,28 @@ enum {
INTEL_AUX_BUFFER_DISABLED = 1 << 1,
};
-uint32_t tex_mocs[] = {
+uint32_t wb_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
[10] = CNL_MOCS_WB,
};
-uint32_t rb_mocs[] = {
+uint32_t pte_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
[10] = CNL_MOCS_PTE,
};
+static uint32_t
+get_tex_mocs(const struct brw_context *brw, struct brw_bo *bo)
+{
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+ return (bo && bo->external ? pte_mocs : wb_mocs)[devinfo->gen];
+}
+
static void
get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
GLenum target, struct isl_view *view,
@@ -244,7 +252,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t offset;
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
- rb_mocs[brw->gen],
+ pte_mocs[brw->gen],
&offset, surf_index,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
@@ -589,7 +597,7 @@ brw_update_texture_surface(struct gl_context *ctx,
aux_usage = ISL_AUX_USAGE_NONE;
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
- tex_mocs[brw->gen],
+ get_tex_mocs(brw, mt->bo),
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
}
@@ -615,7 +623,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
.size = buffer_size,
.format = surface_format,
.stride = pitch,
- .mocs = tex_mocs[brw->gen]);
+ .mocs = get_tex_mocs(brw, bo));
if (bo) {
brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset,
@@ -1164,7 +1172,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
aux_usage = ISL_AUX_USAGE_NONE;
brw_emit_surface_state(brw, irb->mt, target, view, aux_usage,
- tex_mocs[brw->gen],
+ get_tex_mocs(brw, irb->mt->bo),
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER, 0);
@@ -1657,7 +1665,8 @@ update_image_surface(struct brw_context *brw,
view.base_array_layer,
view.array_len));
brw_emit_surface_state(brw, mt, mt->target, view,
- ISL_AUX_USAGE_NONE, tex_mocs[brw->gen],
+ ISL_AUX_USAGE_NONE,
+ get_tex_mocs(brw, mt->bo),
surf_offset, surf_index,
I915_GEM_DOMAIN_SAMPLER,
access == GL_READ_ONLY ? 0 :
--
2.14.3

117
SOURCES/Mesa-MLAA-License-Clarification-Email.txt
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@ -0,0 +1,117 @@ @@ -0,0 +1,117 @@

Subject: RE: Question about Mesa MLAA license
From: Jorge Jimenez <iryoku@gmail.com>
Date: 01/08/2013 12:50 PM
To: Tom Callaway <tcallawa@redhat.com>
CC: "jorge@iryoku.com" <jorge@iryoku.com>

Yes to both questions.
Thanks,
Jorge
From: Tom Callaway <tcallawa@redhat.com>
Sent: January 8, 2013 6:49 PM
To: Jorge Jimenez <iryoku@gmail.com>
CC: jorge@iryoku.com
Subject: Re: Question about Mesa MLAA license
On 01/08/2013 12:39 PM, Jorge Jimenez wrote:
> Hi Tom,
>
> What we meant with that is that we made an exception for clause 2.
> Instead of clause 2, in the case of the Mesa project, you have to name
> the technique Jimenez's MLAA in the config options of Mesa. We did that
> just to allow them to solve license issues. This exception should be for
> the Mesa project, and any project using Mesa, like Fedora.
>
> We want to widespread usage of our MLAA, so we want to avoid any kind of
> license complications. Hope current one is good for Fedora, if not
> please tell, and we'll see what we can do!

Okay, a few more questions:

* If Fedora decides to simply reproduce the quoted statement:
"Uses Jimenez's MLAA. Copyright (C) 2010 by Jorge Jimenez, Belen Masia,
Jose I. Echevarria, Fernando Navarro and Diego Gutierrez."

Specifically, if this is done as part of documentation included with
Mesa, is that sufficient to meet clause 2 even if the Mesa config option
is not set as described in your exception?

* Currently, the Mesa config option for MLAA says: "Morphological
anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default
quality". Is this in compliance with your exception?

Thanks again,

~tom

==
Fedora Project

Subject: RE: Question about Mesa MLAA license
From: Jorge Jimenez <iryoku@gmail.com>
Date: 01/08/2013 12:39 PM
To: "jorge@iryoku.com" <jorge@iryoku.com>, Tom Callaway <tcallawa@redhat.com>

Hi Tom,
What we meant with that is that we made an exception for clause 2.
Instead of clause 2, in the case of the Mesa project, you have to name
the technique Jimenez's MLAA in the config options of Mesa. We did that
just to allow them to solve license issues. This exception should be for
the Mesa project, and any project using Mesa, like Fedora.
We want to widespread usage of our MLAA, so we want to avoid any kind of
license complications. Hope current one is good for Fedora, if not
please tell, and we'll see what we can do!
Cheers,
Jorge
From: Tom Callaway <tcallawa@redhat.com>
Sent: January 8, 2013 6:30 PM
To: jorge@iryoku.com
Subject: Question about Mesa MLAA license
Jorge,

Thanks for all of your fantastic graphics work! I have been auditing
Fedora (a popular distribution of Linux) for license compliance and I
came across your MLAA code in Mesa.

The license says:

* 2. Redistributions in binary form must reproduce the following
statement:
*
* "Uses Jimenez's MLAA. Copyright (C) 2010 by Jorge Jimenez, Belen Masia,
* Jose I. Echevarria, Fernando Navarro and Diego Gutierrez."
*
* Only for use in the Mesa project, this point 2 is filled by naming the
* technique Jimenez's MLAA in the Mesa config options.

That wording is unclear. When you say "Only for use in the Mesa
project...", it seems like you could either be saying:

- This code may only be used as part of Mesa.

OR

- In Mesa, you can comply with clause 2 by simply selecting "Jimenez's
MLAA" in the Mesa config options.

*****

If the first item is true, then we may have to remove the MLAA code from
Fedora's copy of Mesa. However, looking at the license on your SMAA
code, I do not believe it to be the case. Please let me know either way!

Thanks in advance,

Tom Callaway
Fedora Legal

==
Fedora Project

28
SOURCES/make-git-snapshot.sh
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@ -0,0 +1,28 @@ @@ -0,0 +1,28 @@
#!/bin/sh

# Usage: ./make-git-snapshot.sh [COMMIT]
#
# to make a snapshot of the given tag/branch. Defaults to HEAD.
# Point env var REF to a local mesa repo to reduce clone time.

if [ -e /usr/bin/pxz ]; then
XZ=/usr/bin/pxz
else
XZ=/usr/bin/xz
fi

DIRNAME=mesa-$( date +%Y%m%d )

echo REF ${REF:+--reference $REF}
echo DIRNAME $DIRNAME
echo HEAD ${1:-17.2}

rm -rf $DIRNAME

git clone --depth 1 ${REF:+--reference $REF} --branch 17.2 \
git://git.freedesktop.org/git/mesa/mesa $DIRNAME

GIT_DIR=$DIRNAME/.git git archive --format=tar --prefix=$DIRNAME/ ${1:-HEAD} \
| $XZ > $DIRNAME.tar.xz

# rm -rf $DIRNAME

5
SOURCES/make-release-tarball.sh
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@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
#!/bin/sh
#
# usage: make-release-tarball.sh [version]

curl -O ftp://ftp.freedesktop.org/pub/mesa/$1/MesaLib-$1.tar.bz2

328
SOURCES/mesa-10.2-evergreen-big-endian.patch
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@ -0,0 +1,328 @@ @@ -0,0 +1,328 @@
diff -up mesa-20160225/src/gallium/drivers/r600/evergreen_state.c.egbe mesa-20160225/src/gallium/drivers/r600/evergreen_state.c
--- mesa-20160225/src/gallium/drivers/r600/evergreen_state.c.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/r600/evergreen_state.c 2016-02-25 13:06:47.351154059 +1000
@@ -219,7 +219,7 @@ static bool r600_is_sampler_format_suppo
static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
return r600_translate_colorformat(chip, format) != ~0U &&
- r600_translate_colorswap(format) != ~0U;
+ r600_translate_colorswap(chip, format) != ~0U;
}
static bool r600_is_zs_format_supported(enum pipe_format format)
@@ -982,7 +982,8 @@ void evergreen_init_color_surface_rat(st
unsigned format = r600_translate_colorformat(rctx->b.chip_class,
surf->base.format);
unsigned endian = r600_colorformat_endian_swap(format);
- unsigned swap = r600_translate_colorswap(surf->base.format);
+ unsigned swap = r600_translate_colorswap(rctx->b.chip_class,
+ surf->base.format);
unsigned block_size =
align(util_format_get_blocksize(pipe_buffer->format), 4);
unsigned pitch_alignment =
@@ -1143,7 +1144,7 @@ void evergreen_init_color_surface(struct
format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
assert(format != ~0);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(rctx->b.chip_class, surf->base.format);
assert(swap != ~0);
if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
diff -up mesa-20160225/src/gallium/drivers/r600/r600_state.c.egbe mesa-20160225/src/gallium/drivers/r600/r600_state.c
--- mesa-20160225/src/gallium/drivers/r600/r600_state.c.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/r600/r600_state.c 2016-02-25 13:06:47.351154059 +1000
@@ -149,7 +149,7 @@ static bool r600_is_sampler_format_suppo
static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
return r600_translate_colorformat(chip, format) != ~0U &&
- r600_translate_colorswap(format) != ~0U;
+ r600_translate_colorswap(chip, format) != ~0U;
}
static bool r600_is_zs_format_supported(enum pipe_format format)
@@ -927,7 +927,7 @@ static void r600_init_color_surface(stru
format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
assert(format != ~0);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(rctx->b.chip_class, surf->base.format);
assert(swap != ~0);
if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
diff -up mesa-20160225/src/gallium/drivers/r600/r600_state_common.c.egbe mesa-20160225/src/gallium/drivers/r600/r600_state_common.c
--- mesa-20160225/src/gallium/drivers/r600/r600_state_common.c.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/r600/r600_state_common.c 2016-02-25 13:06:47.352154086 +1000
@@ -2704,7 +2704,7 @@ uint32_t r600_translate_colorformat(enum
uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
{
- if (R600_BIG_ENDIAN) {
+ if (0 && R600_BIG_ENDIAN) {
switch(colorformat) {
/* 8-bit buffers. */
case V_0280A0_COLOR_4_4:
diff -up mesa-20160225/src/gallium/drivers/radeon/r600_pipe_common.h.egbe mesa-20160225/src/gallium/drivers/radeon/r600_pipe_common.h
--- mesa-20160225/src/gallium/drivers/radeon/r600_pipe_common.h.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/radeon/r600_pipe_common.h 2016-02-25 13:06:47.352154086 +1000
@@ -576,7 +576,7 @@ struct pipe_surface *r600_create_surface
struct pipe_resource *texture,
const struct pipe_surface *templ,
unsigned width, unsigned height);
-unsigned r600_translate_colorswap(enum pipe_format format);
+unsigned r600_translate_colorswap(enum chip_class chip, enum pipe_format format);
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
diff -up mesa-20160225/src/gallium/drivers/radeon/r600_texture.c.egbe mesa-20160225/src/gallium/drivers/radeon/r600_texture.c
--- mesa-20160225/src/gallium/drivers/radeon/r600_texture.c.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/radeon/r600_texture.c 2016-02-25 13:07:22.903127421 +1000
@@ -1252,10 +1252,215 @@ static void r600_surface_destroy(struct
FREE(surface);
}
-unsigned r600_translate_colorswap(enum pipe_format format)
+static uint32_t evergreen_translate_colorswap(enum pipe_format format)
+{
+ switch (format) {
+ /* 8-bit buffers. */
+ case PIPE_FORMAT_A8_UNORM:
+ case PIPE_FORMAT_A8_SNORM:
+ case PIPE_FORMAT_A8_UINT:
+ case PIPE_FORMAT_A8_SINT:
+ case PIPE_FORMAT_A16_UNORM:
+ case PIPE_FORMAT_A16_SNORM:
+ case PIPE_FORMAT_A16_UINT:
+ case PIPE_FORMAT_A16_SINT:
+ case PIPE_FORMAT_A16_FLOAT:
+ case PIPE_FORMAT_A32_UINT:
+ case PIPE_FORMAT_A32_SINT:
+ case PIPE_FORMAT_A32_FLOAT:
+ case PIPE_FORMAT_R4A4_UNORM:
+ return V_0280A0_SWAP_ALT_REV;
+ case PIPE_FORMAT_I8_UNORM:
+ case PIPE_FORMAT_I8_SNORM:
+ case PIPE_FORMAT_I8_UINT:
+ case PIPE_FORMAT_I8_SINT:
+ case PIPE_FORMAT_L8_UNORM:
+ case PIPE_FORMAT_L8_SNORM:
+ case PIPE_FORMAT_L8_UINT:
+ case PIPE_FORMAT_L8_SINT:
+ case PIPE_FORMAT_L8_SRGB:
+ case PIPE_FORMAT_L16_UNORM:
+ case PIPE_FORMAT_L16_SNORM:
+ case PIPE_FORMAT_L16_UINT:
+ case PIPE_FORMAT_L16_SINT:
+ case PIPE_FORMAT_L16_FLOAT:
+ case PIPE_FORMAT_L32_UINT:
+ case PIPE_FORMAT_L32_SINT:
+ case PIPE_FORMAT_L32_FLOAT:
+ case PIPE_FORMAT_I16_UNORM:
+ case PIPE_FORMAT_I16_SNORM:
+ case PIPE_FORMAT_I16_UINT:
+ case PIPE_FORMAT_I16_SINT:
+ case PIPE_FORMAT_I16_FLOAT:
+ case PIPE_FORMAT_I32_UINT:
+ case PIPE_FORMAT_I32_SINT:
+ case PIPE_FORMAT_I32_FLOAT:
+ case PIPE_FORMAT_R8_UNORM:
+ case PIPE_FORMAT_R8_SNORM:
+ case PIPE_FORMAT_R8_UINT:
+ case PIPE_FORMAT_R8_SINT:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_L4A4_UNORM:
+ case PIPE_FORMAT_A4R4_UNORM:
+ return V_0280A0_SWAP_ALT;
+
+ /* 16-bit buffers. */
+ case PIPE_FORMAT_B5G6R5_UNORM:
+ return V_0280A0_SWAP_STD_REV;
+
+ case PIPE_FORMAT_B5G5R5A1_UNORM:
+ case PIPE_FORMAT_B5G5R5X1_UNORM:
+ return V_0280A0_SWAP_ALT;
+
+ case PIPE_FORMAT_B4G4R4A4_UNORM:
+ case PIPE_FORMAT_B4G4R4X4_UNORM:
+ return V_0280A0_SWAP_ALT;
+
+ case PIPE_FORMAT_Z16_UNORM:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_L8A8_UNORM:
+ case PIPE_FORMAT_L8A8_SNORM:
+ case PIPE_FORMAT_L8A8_UINT:
+ case PIPE_FORMAT_L8A8_SINT:
+ case PIPE_FORMAT_L8A8_SRGB:
+ case PIPE_FORMAT_L16A16_UNORM:
+ case PIPE_FORMAT_L16A16_SNORM:
+ case PIPE_FORMAT_L16A16_UINT:
+ case PIPE_FORMAT_L16A16_SINT:
+ case PIPE_FORMAT_L16A16_FLOAT:
+ case PIPE_FORMAT_L32A32_UINT:
+ case PIPE_FORMAT_L32A32_SINT:
+ case PIPE_FORMAT_L32A32_FLOAT:
+ case PIPE_FORMAT_R8A8_UNORM:
+ case PIPE_FORMAT_R8A8_SNORM:
+ case PIPE_FORMAT_R8A8_UINT:
+ case PIPE_FORMAT_R8A8_SINT:
+ case PIPE_FORMAT_R16A16_UNORM:
+ case PIPE_FORMAT_R16A16_SNORM:
+ case PIPE_FORMAT_R16A16_UINT:
+ case PIPE_FORMAT_R16A16_SINT:
+ case PIPE_FORMAT_R16A16_FLOAT:
+ case PIPE_FORMAT_R32A32_UINT:
+ case PIPE_FORMAT_R32A32_SINT:
+ case PIPE_FORMAT_R32A32_FLOAT:
+ return V_0280A0_SWAP_ALT;
+ case PIPE_FORMAT_R8G8_UNORM:
+ case PIPE_FORMAT_R8G8_SNORM:
+ case PIPE_FORMAT_R8G8_UINT:
+ case PIPE_FORMAT_R8G8_SINT:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_R16_UNORM:
+ case PIPE_FORMAT_R16_SNORM:
+ case PIPE_FORMAT_R16_UINT:
+ case PIPE_FORMAT_R16_SINT:
+ case PIPE_FORMAT_R16_FLOAT:
+ return V_0280A0_SWAP_STD;
+
+ /* 32-bit buffers. */
+
+ case PIPE_FORMAT_A8B8G8R8_SRGB:
+ return V_0280A0_SWAP_STD_REV;
+ case PIPE_FORMAT_B8G8R8A8_SRGB:
+ return V_0280A0_SWAP_ALT;
+
+ case PIPE_FORMAT_B8G8R8A8_UNORM:
+ case PIPE_FORMAT_B8G8R8X8_UNORM:
+ return V_0280A0_SWAP_ALT;
+
+ case PIPE_FORMAT_A8R8G8B8_UNORM:
+ case PIPE_FORMAT_X8R8G8B8_UNORM:
+ return V_0280A0_SWAP_ALT_REV;
+ case PIPE_FORMAT_R8G8B8A8_SNORM:
+ case PIPE_FORMAT_R8G8B8A8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_UNORM:
+ case PIPE_FORMAT_R8G8B8X8_SNORM:
+ case PIPE_FORMAT_R8G8B8X8_SRGB:
+ case PIPE_FORMAT_R8G8B8X8_UINT:
+ case PIPE_FORMAT_R8G8B8X8_SINT:
+ case PIPE_FORMAT_R8G8B8A8_SINT:
+ case PIPE_FORMAT_R8G8B8A8_UINT:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_A8B8G8R8_UNORM:
+ case PIPE_FORMAT_X8B8G8R8_UNORM:
+ /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
+ return V_0280A0_SWAP_STD_REV;
+
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_R10G10B10A2_UNORM:
+ case PIPE_FORMAT_R10G10B10X2_SNORM:
+ case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+ case PIPE_FORMAT_R10G10B10A2_UINT:
+ return V_0280A0_SWAP_STD;
+
+ case PIPE_FORMAT_B10G10R10A2_UNORM:
+ case PIPE_FORMAT_B10G10R10A2_UINT:
+ case PIPE_FORMAT_B10G10R10X2_UNORM:
+ return V_0280A0_SWAP_ALT;
+
+ case PIPE_FORMAT_R11G11B10_FLOAT:
+ case PIPE_FORMAT_R16G16_UNORM:
+ case PIPE_FORMAT_R16G16_SNORM:
+ case PIPE_FORMAT_R16G16_FLOAT:
+ case PIPE_FORMAT_R16G16_UINT:
+ case PIPE_FORMAT_R16G16_SINT:
+ case PIPE_FORMAT_R32_UINT:
+ case PIPE_FORMAT_R32_SINT:
+ case PIPE_FORMAT_R32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT:
+ return V_0280A0_SWAP_STD;
+
+ /* 64-bit buffers. */
+ case PIPE_FORMAT_R32G32_FLOAT:
+ case PIPE_FORMAT_R32G32_UINT:
+ case PIPE_FORMAT_R32G32_SINT:
+ case PIPE_FORMAT_R16G16B16A16_UNORM:
+ case PIPE_FORMAT_R16G16B16A16_SNORM:
+ case PIPE_FORMAT_R16G16B16A16_UINT:
+ case PIPE_FORMAT_R16G16B16A16_SINT:
+ case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UNORM:
+ case PIPE_FORMAT_R16G16B16X16_SNORM:
+ case PIPE_FORMAT_R16G16B16X16_FLOAT:
+ case PIPE_FORMAT_R16G16B16X16_UINT:
+ case PIPE_FORMAT_R16G16B16X16_SINT:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+
+ /* 128-bit buffers. */
+ case PIPE_FORMAT_R32G32B32A32_FLOAT:
+ case PIPE_FORMAT_R32G32B32A32_SNORM:
+ case PIPE_FORMAT_R32G32B32A32_UNORM:
+ case PIPE_FORMAT_R32G32B32A32_SINT:
+ case PIPE_FORMAT_R32G32B32A32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_FLOAT:
+ case PIPE_FORMAT_R32G32B32X32_UINT:
+ case PIPE_FORMAT_R32G32B32X32_SINT:
+ return V_0280A0_SWAP_STD;
+ default:
+ R600_ERR("unsupported colorswap format %d\n", format);
+ return ~0U;
+ }
+ return ~0U;
+}
+
+unsigned r600_translate_colorswap(enum chip_class chip, enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
+#ifdef PIPE_ARCH_BIG_ENDIAN
+ if (chip == EVERGREEN) {
+ unsigned ret = evergreen_translate_colorswap(format);
+ if (ret != ~0U)
+ return ret;
+ }
+#endif
+
#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
@@ -1411,6 +1616,10 @@ void evergreen_do_fast_color_clear(struc
if (rctx->render_cond)
return;
+#ifdef PIPE_ARCH_BIG_ENDIAN
+ return false; /* broken; overkill to just disable them, but */
+#endif
+
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
diff -up mesa-20160225/src/gallium/drivers/radeonsi/si_state.c.egbe mesa-20160225/src/gallium/drivers/radeonsi/si_state.c
--- mesa-20160225/src/gallium/drivers/radeonsi/si_state.c.egbe 2016-02-22 21:42:41.000000000 +1000
+++ mesa-20160225/src/gallium/drivers/radeonsi/si_state.c 2016-02-25 13:06:47.353154114 +1000
@@ -1966,7 +1966,7 @@ static bool si_is_vertex_format_supporte
static bool si_is_colorbuffer_format_supported(enum pipe_format format)
{
return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
- r600_translate_colorswap(format) != ~0U;
+ r600_translate_colorswap(0, format) != ~0U;
}
static bool si_is_zs_format_supported(enum pipe_format format)
@@ -2249,7 +2249,7 @@ static void si_initialize_color_surface(
R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
}
assert(format != V_028C70_COLOR_INVALID);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(0, surf->base.format);
if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = V_028C70_ENDIAN_NONE;
} else {

194
SOURCES/mesa-17.3-final.patch
Unescape View File

@ -0,0 +1,194 @@ @@ -0,0 +1,194 @@
diff --git a/VERSION b/VERSION
index d3b2c4f..afbe633 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.2
+17.2.3
diff --git a/docs/relnotes/17.2.3.html b/docs/relnotes/17.2.3.html
new file mode 100644
index 0000000..6e2aea6
--- /dev/null
+++ b/docs/relnotes/17.2.3.html
@@ -0,0 +1,181 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.2.3 Release Notes / October 19, 2017</h1>
+
+<p>
+Mesa 17.2.3 is a bug fix release which fixes bugs found since the 17.2.2 release.
+</p>
+<p>
+Mesa 17.2.3 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+fb305eecfeec1fd771fdc96fff973c51871f7bd35fd2bd56cacc27b4b8823220 mesa-17.2.3.tar.gz
+a0b0ec8f7b24dd044d7ab30a8c7e6d3767521e245f88d4ed5dd93315dc56f837 mesa-17.2.3.tar.xz
+</pre>
+
+
+<h2>New features</h2>
+<p>None</p>
+
+
+<h2>Bug fixes</h2>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101832">Bug 101832</a> - [PATCH][regression][bisect] Xorg fails to start after f50aa21456d82c8cb6fbaa565835f1acc1720a5d</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102852">Bug 102852</a> - Scons: Support the new Scons 3.0.0</li>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=102940">Bug 102940</a> - Regression: Vulkan KMS rendering crashes since 17.2</li>
+
+</ul>
+
+
+<h2>Changes</h2>
+
+<p>Alex Smith (1):</p>
+<ul>
+ <li>radv: Add R16G16B16A16_SNORM fast clear support</li>
+</ul>
+
+<p>Bas Nieuwenhuizen (2):</p>
+<ul>
+ <li>nir/spirv: Allow loop breaks in a switch body.</li>
+ <li>radv: Only set the MTYPE flags on GFX9+.</li>
+</ul>
+
+<p>Ben Crocker (4):</p>
+<ul>
+ <li>gallivm: fix typo in debug_printf message</li>
+ <li>gallivm: allow additional llc options</li>
+ <li>gallivm/ppc64le: adjust VSX code generation control.</li>
+ <li>gallivm/ppc64le: allow environmental control of Altivec code generation</li>
+</ul>
+
+<p>Daniel Stone (2):</p>
+<ul>
+ <li>egl/wayland: Check queryImage return for wl_buffer</li>
+ <li>egl/wayland: Don't use dmabuf with no modifiers</li>
+</ul>
+
+<p>Dave Airlie (2):</p>
+<ul>
+ <li>radv: emit fmuladd instead of fma to llvm.</li>
+ <li>radv: lower ffma in nir.</li>
+</ul>
+
+<p>Emil Velikov (6):</p>
+<ul>
+ <li>cherry-ignore: add "anv: Remove unreachable cases from isl_format_for_size"</li>
+ <li>cherry-ignore: add "anv/wsi: Allocate enough memory for the entire image"</li>
+ <li>swr/rast: do not crash on NULL strings returned by getenv</li>
+ <li>wayland-drm: use a copy of the wayland_drm_callbacks struct</li>
+ <li>eglmesaext: add forward declaration for struct wl_buffers</li>
+ <li>Update version to 17.2.3</li>
+</ul>
+
+<p>Eric Engestrom (1):</p>
+<ul>
+ <li>scons: use python3-compatible print()</li>
+</ul>
+
+<p>Ilia Mirkin (2):</p>
+<ul>
+ <li>nv50/ir: fix 64-bit integer shifts</li>
+ <li>nv50,nvc0: fix push hint logic in presence of a start offset</li>
+</ul>
+
+<p>Jason Ekstrand (6):</p>
+<ul>
+ <li>intel/compiler: Don't cmod propagate into a saturated operation</li>
+ <li>intel/compiler: Don't propagate cmod into integer multiplies</li>
+ <li>glsl/blob: Return false from ensure_can_read on overrun</li>
+ <li>glsl/blob: Return false from grow_to_fit if we've ever failed</li>
+ <li>nir/opcodes: Fix constant-folding of ufind_msb</li>
+ <li>nir: Get rid of the variable on vote intrinsics</li>
+</ul>
+
+<p>Juan A. Suarez Romero (1):</p>
+<ul>
+ <li>docs: add sha256 checksums for 17.2.2</li>
+</ul>
+
+<p>Józef Kucia (3):</p>
+<ul>
+ <li>anv: Fix vkCmdFillBuffer()</li>
+ <li>spirv: Fix SpvOpAtomicISub</li>
+ <li>anv: Do not assert() on VK_ATTACHMENT_UNUSED</li>
+</ul>
+
+<p>Leo Liu (3):</p>
+<ul>
+ <li>st/va: use pipe transfer_map to map upload buffer</li>
+ <li>st/vdpau: don't re-allocate interlaced buffer with packed YUV format</li>
+ <li>st/va: don't re-allocate interlaced buffer with pakced format</li>
+</ul>
+
+<p>Lionel Landwerlin (4):</p>
+<ul>
+ <li>intel: compiler: vec4: add missing default 0 lod</li>
+ <li>anv/cmd_buffer: fix push descriptors with set &gt; 0</li>
+ <li>anv/cmd_buffer: Reset state in cmd_buffer_destroy</li>
+ <li>anv: bo_cache: allow importing a BO larger than needed</li>
+</ul>
+
+<p>Marek Olšák (3):</p>
+<ul>
+ <li>mesa: fix texture updates for ATI_fragment_shader</li>
+ <li>st/mesa: don't use pipe_surface for passing information about EGLImage</li>
+ <li>glsl_to_tgsi: fix instruction order for bindless textures</li>
+</ul>
+
+<p>Nicolai Hähnle (14):</p>
+<ul>
+ <li>st/glsl_to_tgsi: fix conditional assignments to packed shader outputs</li>
+ <li>amd/common: fix build_cube_select</li>
+ <li>radeonsi/gfx9: fix geometry shaders without output vertices</li>
+ <li>util/queue: fix a race condition in the fence code</li>
+ <li>glsl/lower_instruction: handle denorms and overflow in ldexp correctly</li>
+ <li>radeonsi: move current_rast_prim to r600_common_context</li>
+ <li>radeonsi: don't discard points and lines</li>
+ <li>radeonsi: deduce rast_prim correctly for tessellation point mode</li>
+ <li>radeonsi: fix maximum advertised point size / line width</li>
+ <li>st/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS</li>
+ <li>st/glsl_to_tgsi: fix indirect access to 64-bit integer</li>
+ <li>st/glsl_to_tgsi: fix a use-after-free in merge_two_dsts</li>
+ <li>radeonsi: clamp depth comparison value only for fixed point formats</li>
+ <li>radeonsi: clamp border colors for upgraded depth textures</li>
+</ul>
+
+<p>Rob Clark (2):</p>
+<ul>
+ <li>freedreno/a5xx: align height to GMEM</li>
+ <li>freedreno/a5xx: fix missing restore state</li>
+</ul>
+
+
+</div>
+</body>
+</html>

156
SOURCES/mesa-8.0-llvmpipe-shmget.patch
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@ -0,0 +1,156 @@ @@ -0,0 +1,156 @@
diff -up mesa-20120424/src/gallium/state_trackers/dri/sw/drisw.c.jx mesa-20120424/src/gallium/state_trackers/dri/sw/drisw.c
--- mesa-20120424/src/gallium/state_trackers/dri/sw/drisw.c.jx 2012-04-24 07:37:03.000000000 -0400
+++ mesa-20120424/src/gallium/state_trackers/dri/sw/drisw.c 2012-05-16 13:30:36.596312047 -0400
@@ -252,8 +252,6 @@ drisw_update_tex_buffer(struct dri_drawa
struct pipe_transfer *transfer;
char *map;
int x, y, w, h;
- int ximage_stride, line;
- int cpp = util_format_get_blocksize(res->format);
get_drawable_info(dPriv, &x, &y, &w, &h);
@@ -266,14 +264,6 @@ drisw_update_tex_buffer(struct dri_drawa
/* Copy the Drawable content to the mapped texture buffer */
get_image(dPriv, x, y, w, h, map);
- /* The pipe transfer has a pitch rounded up to the nearest 64 pixels. */
- ximage_stride = w * cpp;
- for (line = h-1; line; --line) {
- memmove(&map[line * transfer->stride],
- &map[line * ximage_stride],
- ximage_stride);
- }
-
pipe_transfer_unmap(pipe, transfer);
pipe_transfer_destroy(pipe, transfer);
}
diff -up mesa-20120424/src/glx/drisw_glx.c.jx mesa-20120424/src/glx/drisw_glx.c
--- mesa-20120424/src/glx/drisw_glx.c.jx 2012-04-24 07:37:03.000000000 -0400
+++ mesa-20120424/src/glx/drisw_glx.c 2012-05-16 13:29:25.087965268 -0400
@@ -24,6 +24,9 @@
#if defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL)
#include <X11/Xlib.h>
+#include <sys/ipc.h>
+#include <sys/shm.h>
+#include <X11/extensions/XShm.h>
#include "glxclient.h"
#include <dlfcn.h>
#include "dri_common.h"
@@ -206,6 +209,96 @@ swrastPutImage(__DRIdrawable * draw, int
ximage->data = NULL;
}
+static int shm_error;
+
+static int
+shm_handler(Display *d, XErrorEvent *e)
+{
+ shm_error = 1;
+ return 0;
+}
+
+static int
+align(int value, int alignment)
+{
+ return (value + alignment - 1) & ~(alignment - 1);
+}
+
+/*
+ * Slight fast path. Short of changing how texture memory is allocated, we
+ * have two options for getting the pixels out. GetImage is clamped by the
+ * server's write buffer size, so you end up doing lots of relatively small
+ * requests (128k each or so), with two memcpys: down into the kernel, and
+ * then back up. ShmGetImage is one big blit into the shm segment (which
+ * could be GPU DMA, in principle) and then another one here.
+ */
+static Bool
+swrastShmGetImage(__DRIdrawable *read, char *data, struct drisw_drawable *prp)
+{
+ __GLXDRIdrawable *pread = &(prp->base);
+ Display *dpy = pread->psc->dpy;
+ XImage *ximage = prp->ximage;
+ unsigned long image_size = ximage->height * ximage->bytes_per_line;
+ Bool ret = 0;
+ XShmSegmentInfo seg = { 0, -1, (void *)-1, 0 };
+ int (*old_handler)(Display *, XErrorEvent *);
+
+ if (!XShmQueryExtension(dpy))
+ goto out;
+
+ /* image setup */
+ seg.shmid = shmget(IPC_PRIVATE, image_size, IPC_CREAT | 0777);
+ if (seg.shmid < 0)
+ goto out;
+
+ seg.shmaddr = shmat(seg.shmid, NULL, 0);
+ if (seg.shmaddr == (void *)-1)
+ goto out;
+
+ XSync(dpy, 0);
+ old_handler = XSetErrorHandler(shm_handler);
+ XShmAttach(dpy, &seg);
+ XSync(dpy, 0);
+ XSetErrorHandler(old_handler);
+ if (shm_error)
+ goto out;
+
+ ximage->data = seg.shmaddr;
+ ximage->obdata = &seg;
+ if (!XShmGetImage(dpy, pread->xDrawable, ximage, 0, 0, -1))
+ goto out;
+
+ /*
+ * ShmGetImage doesn't actually pay attention to ->bytes_per_line.
+ * We have to compensate for this somewhere since llvmpipe's natural
+ * tile width is 64. Do it here so we don't have to undo it with a
+ * bunch of memmove in the driver.
+ */
+ do {
+ int i;
+ char *src = ximage->data;
+ int dst_width = align(ximage->width * ximage->bits_per_pixel / 8, 256);
+
+ for (i = 0; i < ximage->height; i++) {
+ memcpy(data, src, ximage->bytes_per_line);
+ data += dst_width;
+ src += ximage->bytes_per_line;
+ }
+ } while (0);
+ ret = 1;
+
+out:
+ ximage->obdata = NULL;
+ ximage->data = NULL;
+ shm_error = 0;
+ XShmDetach(dpy, &seg);
+ if (seg.shmaddr != (void *)-1)
+ shmdt(seg.shmaddr);
+ if (seg.shmid > -1)
+ shmctl(seg.shmid, IPC_RMID, NULL);
+ return ret;
+}
+
static void
swrastGetImage(__DRIdrawable * read,
int x, int y, int w, int h,
@@ -220,11 +313,17 @@ swrastGetImage(__DRIdrawable * read,
readable = pread->xDrawable;
ximage = prp->ximage;
- ximage->data = data;
ximage->width = w;
ximage->height = h;
ximage->bytes_per_line = bytes_per_line(w * ximage->bits_per_pixel, 32);
+ /* XXX check dimensions, if any caller ever sub-images */
+ if (swrastShmGetImage(read, data, prp))
+ return;
+
+ /* shm failed, fall back to protocol */
+ ximage->data = data;
+
XGetSubImage(dpy, readable, x, y, w, h, ~0L, ZPixmap, ximage, 0, 0);
ximage->data = NULL;

13
SOURCES/mesa-8.0.1-fix-16bpp.patch
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@ -0,0 +1,13 @@ @@ -0,0 +1,13 @@
diff -up Mesa-8.0.1/src/mesa/state_tracker/st_manager.c.jx Mesa-8.0.1/src/mesa/state_tracker/st_manager.c
--- Mesa-8.0.1/src/mesa/state_tracker/st_manager.c.jx 2012-02-14 18:44:00.000000000 -0500
+++ Mesa-8.0.1/src/mesa/state_tracker/st_manager.c 2012-04-02 12:02:14.613964417 -0400
@@ -528,6 +528,9 @@ st_context_teximage(struct st_context_if
if (util_format_get_component_bits(internal_format,
UTIL_FORMAT_COLORSPACE_RGB, 3) > 0)
internalFormat = GL_RGBA;
+ else if (util_format_get_component_bits(internal_format,
+ UTIL_FORMAT_COLORSPACE_RGB, 0) == 5)
+ internalFormat = GL_RGB5;
else
internalFormat = GL_RGB;

36
SOURCES/mesa-9.2-hardware-float.patch
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@ -0,0 +1,36 @@ @@ -0,0 +1,36 @@
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 5ec1df6..a0406fc 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -306,6 +306,13 @@ llvmpipe_is_format_supported( struct pipe_screen *_screen,
if (!format_desc)
return FALSE;
+ if ((bind & PIPE_BIND_RENDER_TARGET) &&
+ format != PIPE_FORMAT_R9G9B9E5_FLOAT &&
+ format != PIPE_FORMAT_R11G11B10_FLOAT &&
+ util_format_is_float(format)) {
+ return FALSE;
+ }
+
assert(target == PIPE_BUFFER ||
target == PIPE_TEXTURE_1D ||
target == PIPE_TEXTURE_1D_ARRAY ||
diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c
index 937035e..2f5e571 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -291,6 +291,13 @@ softpipe_is_format_supported( struct pipe_screen *screen,
if (!format_desc)
return FALSE;
+ if ((bind & PIPE_BIND_RENDER_TARGET) &&
+ format != PIPE_FORMAT_R9G9B9E5_FLOAT &&
+ format != PIPE_FORMAT_R11G11B10_FLOAT &&
+ util_format_is_float(format)) {
+ return FALSE;
+ }
+
if (sample_count > 1)
return FALSE;

12
SOURCES/nv50-fix-build.patch
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@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
diff -up mesa-20140827/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp.fixbuild mesa-20140827/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
--- mesa-20140827/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp.fixbuild 2014-08-27 15:33:21.858830514 +1000
+++ mesa-20140827/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp 2014-08-27 15:33:33.193830514 +1000
@@ -739,7 +739,7 @@ Instruction::clone(ClonePolicy<Function>
if (!i)
i = new_Instruction(pol.context(), op, dType);
#ifndef NDEBUG // non-conformant assert, so this is required
- assert(typeid(*i) == typeid(*this));
+ //assert(typeid(*i) == typeid(*this));
#endif
pol.set<Instruction>(this, i);

55
SOURCES/sanitize-tarball.sh
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@ -0,0 +1,55 @@ @@ -0,0 +1,55 @@
#!/bin/sh
#
# usage: sanitize-tarball.sh [tarball]

if [ "x$1" = "x" ]; then
echo "Usage: sanitize-tarball.sh [tarball]"
exit 1
fi

if [ -e /usr/bin/pxz ]; then
XZ=/usr/bin/pxz
else
XZ=/usr/bin/xz
fi

dirname=$(basename $(basename "$1" .tar.bz2) .tar.xz)

tar xf "$1"
pushd $dirname

cat > src/gallium/auxiliary/vl/vl_mpeg12_decoder.c << EOF
#include "vl_mpeg12_decoder.h"
struct pipe_video_codec *
vl_create_mpeg12_decoder(struct pipe_context *context,
const struct pipe_video_codec *templat)
{
return NULL;
}
EOF

cat > src/gallium/auxiliary/vl/vl_decoder.c << EOF
#include "vl_decoder.h"
bool vl_profile_supported(struct pipe_screen *screen,
enum pipe_video_profile profile,
enum pipe_video_entrypoint entrypoint)
{
return false;
}

int
vl_level_supported(struct pipe_screen *screen, enum pipe_video_profile profile)
{
return 0;
}

struct pipe_video_codec *
vl_create_decoder(struct pipe_context *pipe,
const struct pipe_video_codec *templat)
{
return NULL;
}
EOF

popd
tar cf - $dirname | $XZ > $dirname.tar.xz

1034
SPECS/mesa.spec
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