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79 lines
3.7 KiB
79 lines
3.7 KiB
7 years ago
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From 0fda9532e2f187f03b45ad29d2d151c500d64533 Mon Sep 17 00:00:00 2001
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From: Anuj Phogat <anuj.phogat@gmail.com>
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Date: Wed, 10 Jan 2018 15:51:02 -0800
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Subject: [PATCH 2/2] intel: Add more Coffeelake PCI IDs
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Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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---
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intel/intel_chipset.h | 30 +++++++++++++++++++++++-------
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1 file changed, 23 insertions(+), 7 deletions(-)
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
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index d81b1646..3818e71e 100644
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--- a/intel/intel_chipset.h
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+++ b/intel/intel_chipset.h
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@@ -223,15 +223,23 @@
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#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
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#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
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+#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
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#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
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#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
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#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
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+#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
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#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
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#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
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-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
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-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
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-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
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-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
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+#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
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+#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
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+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
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+#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
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+#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
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+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
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+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
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+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
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+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
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+#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
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#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
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#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
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@@ -477,17 +485,25 @@
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#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
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- (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3)
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+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
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#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
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-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
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+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
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- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
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+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
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#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
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IS_CFL_H(devid) || \
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--
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2.14.3
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