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118 lines
3.4 KiB
118 lines
3.4 KiB
5 years ago
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From 70a1ae89be6b9f9a535f1fbaff3e4b1c4bb46d4a Mon Sep 17 00:00:00 2001
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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Date: Fri, 1 Feb 2019 23:43:01 -0800
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Subject: [PATCH libdrm] intel: sync i915_pciids.h with kernel
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Straight copy from the kernel file.
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Add more PCI Device IDs for Coffee Lake, Ice Lake,
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and Amber Lake. It also include a reorg on Whiskey Lake IDs.
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Align with kernel commits:
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5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
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03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
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c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
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c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")
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Cc: José Roberto de Souza <jose.souza@intel.com>
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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---
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intel/i915_pciids.h | 29 +++++++++++++++++++++--------
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1 file changed, 21 insertions(+), 8 deletions(-)
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diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
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index fd965ffb..d2fad7b0 100644
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--- a/intel/i915_pciids.h
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+++ b/intel/i915_pciids.h
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@@ -365,16 +365,20 @@
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INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
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/* AML/KBL Y GT2 */
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-#define INTEL_AML_GT2_IDS(info) \
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+#define INTEL_AML_KBL_GT2_IDS(info) \
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INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
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INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
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+/* AML/CFL Y GT2 */
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+#define INTEL_AML_CFL_GT2_IDS(info) \
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+ INTEL_VGA_DEVICE(0x87CA, info)
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+
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#define INTEL_KBL_IDS(info) \
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INTEL_KBL_GT1_IDS(info), \
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INTEL_KBL_GT2_IDS(info), \
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INTEL_KBL_GT3_IDS(info), \
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INTEL_KBL_GT4_IDS(info), \
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- INTEL_AML_GT2_IDS(info)
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+ INTEL_AML_KBL_GT2_IDS(info)
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/* CFL S */
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#define INTEL_CFL_S_GT1_IDS(info) \
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@@ -390,6 +394,9 @@
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INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
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/* CFL H */
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+#define INTEL_CFL_H_GT1_IDS(info) \
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+ INTEL_VGA_DEVICE(0x3E9C, info)
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+
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#define INTEL_CFL_H_GT2_IDS(info) \
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INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
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INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
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@@ -407,27 +414,29 @@
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/* WHL/CFL U GT1 */
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#define INTEL_WHL_U_GT1_IDS(info) \
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- INTEL_VGA_DEVICE(0x3EA1, info)
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+ INTEL_VGA_DEVICE(0x3EA1, info), \
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+ INTEL_VGA_DEVICE(0x3EA4, info)
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/* WHL/CFL U GT2 */
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#define INTEL_WHL_U_GT2_IDS(info) \
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- INTEL_VGA_DEVICE(0x3EA0, info)
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+ INTEL_VGA_DEVICE(0x3EA0, info), \
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+ INTEL_VGA_DEVICE(0x3EA3, info)
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/* WHL/CFL U GT3 */
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#define INTEL_WHL_U_GT3_IDS(info) \
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- INTEL_VGA_DEVICE(0x3EA2, info), \
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- INTEL_VGA_DEVICE(0x3EA3, info), \
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- INTEL_VGA_DEVICE(0x3EA4, info)
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+ INTEL_VGA_DEVICE(0x3EA2, info)
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#define INTEL_CFL_IDS(info) \
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INTEL_CFL_S_GT1_IDS(info), \
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INTEL_CFL_S_GT2_IDS(info), \
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+ INTEL_CFL_H_GT1_IDS(info), \
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INTEL_CFL_H_GT2_IDS(info), \
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INTEL_CFL_U_GT2_IDS(info), \
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INTEL_CFL_U_GT3_IDS(info), \
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INTEL_WHL_U_GT1_IDS(info), \
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INTEL_WHL_U_GT2_IDS(info), \
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- INTEL_WHL_U_GT3_IDS(info)
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+ INTEL_WHL_U_GT3_IDS(info), \
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+ INTEL_AML_CFL_GT2_IDS(info)
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/* CNL */
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#define INTEL_CNL_IDS(info) \
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@@ -452,9 +461,13 @@
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INTEL_VGA_DEVICE(0x8A51, info), \
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INTEL_VGA_DEVICE(0x8A5C, info), \
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INTEL_VGA_DEVICE(0x8A5D, info), \
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+ INTEL_VGA_DEVICE(0x8A59, info), \
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+ INTEL_VGA_DEVICE(0x8A58, info), \
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INTEL_VGA_DEVICE(0x8A52, info), \
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INTEL_VGA_DEVICE(0x8A5A, info), \
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INTEL_VGA_DEVICE(0x8A5B, info), \
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+ INTEL_VGA_DEVICE(0x8A57, info), \
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+ INTEL_VGA_DEVICE(0x8A56, info), \
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INTEL_VGA_DEVICE(0x8A71, info), \
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INTEL_VGA_DEVICE(0x8A70, info)
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--
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2.20.1
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