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94 lines
3.5 KiB
94 lines
3.5 KiB
6 years ago
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From 7b12381723021fd5fbcf761e6832dd16a14f52d4 Mon Sep 17 00:00:00 2001
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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Date: Wed, 7 Feb 2018 22:46:43 -0800
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Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs.
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Let's sync CNL ids with Spec and kernel.
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Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
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Add Cannonlake PCI IDs for another SKU.")' and
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commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'
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Cc: James Ausmus <james.ausmus@intel.com>
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Cc: Lucas De Marchi <lucas.demarchi@intel.com>
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Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
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Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
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---
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intel/intel_chipset.h | 52 +++++++++++++++++++++++--------------------
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1 file changed, 28 insertions(+), 24 deletions(-)
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
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index 3818e71e..01d250e8 100644
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--- a/intel/intel_chipset.h
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+++ b/intel/intel_chipset.h
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@@ -241,16 +241,20 @@
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#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
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#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
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-#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
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-#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
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-#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
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-#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
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-#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
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+#define PCI_CHIP_CANNONLAKE_0 0x5A51
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+#define PCI_CHIP_CANNONLAKE_1 0x5A59
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+#define PCI_CHIP_CANNONLAKE_2 0x5A41
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+#define PCI_CHIP_CANNONLAKE_3 0x5A49
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+#define PCI_CHIP_CANNONLAKE_4 0x5A52
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+#define PCI_CHIP_CANNONLAKE_5 0x5A5A
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+#define PCI_CHIP_CANNONLAKE_6 0x5A42
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+#define PCI_CHIP_CANNONLAKE_7 0x5A4A
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+#define PCI_CHIP_CANNONLAKE_8 0x5A50
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+#define PCI_CHIP_CANNONLAKE_9 0x5A40
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+#define PCI_CHIP_CANNONLAKE_10 0x5A54
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+#define PCI_CHIP_CANNONLAKE_11 0x5A5C
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+#define PCI_CHIP_CANNONLAKE_12 0x5A44
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+#define PCI_CHIP_CANNONLAKE_13 0x5A4C
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I915_GM || \
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@@ -515,20 +519,20 @@
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IS_GEMINILAKE(devid) || \
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IS_COFFEELAKE(devid))
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-#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
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- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
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- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
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- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
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- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
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- (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
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-
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-#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
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- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
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- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
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- (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
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-
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-#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
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- IS_CNL_Y(devid))
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+#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_1 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_2 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_3 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_4 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_5 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_6 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_7 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_8 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_9 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_10 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_11 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_12 || \
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+ (devid) == PCI_CHIP_CANNONLAKE_13)
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#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
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--
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2.17.1
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