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126 lines
5.0 KiB
126 lines
5.0 KiB
commit e43de63c8fd11a15d7c6c852747c81664c0beb2a |
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Author: Alan Modra <amodra@gmail.com> |
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Date: Thu May 19 00:10:35 2016 +0930 |
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Fix powerpc subis range |
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* ppc-opc.c: Formatting. |
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(NSISIGNOPT): Define. |
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(powerpc_opcodes <subis>): Use NSISIGNOPT. |
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### a/opcodes/ChangeLog |
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### b/opcodes/ChangeLog |
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## -1,3 +1,9 @@ |
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+2016-05-19 Alan Modra <amodra@gmail.com> |
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+ |
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+ * ppc-opc.c: Formatting. |
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+ (NSISIGNOPT): Define. |
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+ (powerpc_opcodes <subis>): Use NSISIGNOPT. |
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+ |
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2016-05-18 Maciej W. Rozycki <macro@imgtec.com> |
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* mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, |
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--- a/opcodes/ppc-opc.c |
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+++ b/opcodes/ppc-opc.c |
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@@ -186,25 +186,25 @@ const struct powerpc_operand powerpc_operands[] = |
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This sets the y bit of the BO field appropriately. */ |
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#define BDM BDA + 1 |
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{ 0xfffc, 0, insert_bdm, extract_bdm, |
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- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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/* The BD field in a B form instruction when the - modifier is used |
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and absolute address is used. */ |
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#define BDMA BDM + 1 |
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{ 0xfffc, 0, insert_bdm, extract_bdm, |
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- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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/* The BD field in a B form instruction when the + modifier is used. |
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This sets the y bit of the BO field appropriately. */ |
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#define BDP BDMA + 1 |
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{ 0xfffc, 0, insert_bdp, extract_bdp, |
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- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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/* The BD field in a B form instruction when the + modifier is used |
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and absolute addressing is used. */ |
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#define BDPA BDP + 1 |
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{ 0xfffc, 0, insert_bdp, extract_bdp, |
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- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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/* The BF field in an X or XL form instruction. */ |
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#define BF BDPA + 1 |
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@@ -414,7 +414,8 @@ const struct powerpc_operand powerpc_operands[] = |
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/* Power4 version for mfcr. */ |
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#define FXM4 FXM + 1 |
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- { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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+ { 0xff, 12, insert_fxm, extract_fxm, |
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+ PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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/* If the FXM4 operand is ommitted, use the sentinel value -1. */ |
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{ -1, -1, NULL, NULL, 0}, |
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@@ -493,10 +494,16 @@ const struct powerpc_operand powerpc_operands[] = |
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SI field, only negated. */ |
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#define NSI NBI + 1 |
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{ 0xffff, 0, insert_nsi, extract_nsi, |
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- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
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+ |
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+ /* The NSI field in a D form instruction when we accept a wide range |
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+ of positive values. */ |
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+#define NSISIGNOPT NSI + 1 |
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+ { 0xffff, 0, NULL, NULL, |
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+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
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/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
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-#define RA NSI + 1 |
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+#define RA NSISIGNOPT + 1 |
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#define RA_MASK (0x1f << 16) |
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{ 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
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@@ -601,7 +608,7 @@ const struct powerpc_operand powerpc_operands[] = |
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SCLSCI8 field, only negated. */ |
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#define SCLSCI8N SCLSCI8 + 1 |
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{ 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, |
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- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
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+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
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/* The SD field of the SD4 form instruction. */ |
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#define SE_SD SCLSCI8N + 1 |
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@@ -690,7 +697,8 @@ const struct powerpc_operand powerpc_operands[] = |
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/* The TBR field in an XFX form instruction. This is like the SPR |
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field, but it is optional. */ |
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#define TBR SV + 1 |
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- { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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+ { 0x3ff, 11, insert_tbr, extract_tbr, |
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+ PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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/* If the TBR operand is ommitted, use the value 268. */ |
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{ -1, 268, NULL, NULL, 0}, |
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@@ -874,12 +882,12 @@ const struct powerpc_operand powerpc_operands[] = |
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/* The VLESIMM field in a D form instruction. */ |
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#define VLESIMM URC + 1 |
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{ 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, |
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- PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
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+ PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
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/* The VLENSIMM field in a D form instruction. */ |
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#define VLENSIMM VLESIMM + 1 |
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{ 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, |
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- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
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+ PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
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/* The VLEUIMM field in a D form instruction. */ |
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#define VLEUIMM VLENSIMM + 1 |
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@@ -3878,7 +3886,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}}, |
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{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, |
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{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, |
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-{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, |
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+{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSISIGNOPT}}, |
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{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, |
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{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}},
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