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commit 11a0cf2ec0ed6e70ff25e9a50c2223dcd98c1c10 |
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Author: Peter Bergner <bergner@vnet.ibm.com> |
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Date: Fri Jun 19 17:17:07 2015 -0500 |
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Allow for optional operands with non-zero default values. |
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ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand |
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with the value of either a 0 or 1. It also defines an extended mnemonic |
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with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1". |
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I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the |
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problem is, optional operands that are ommitted always default to the |
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value 0, which is wrong in this case. I have added support for allowing |
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non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE |
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that specifies that the default operand value to be used is stored in the |
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SHIFT field of the operand field immediately following this one. |
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This fixes the rfebb issue. I also fixed the mftb and mfcr instructions |
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so they use the same mechanism. This allows us to flag invalid uses of |
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mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd]. |
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include/opcode/ |
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* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. |
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(ppc_optional_operand_value): New inline function. |
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opcodes/ |
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* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
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* ppc-opc.c (FXM4): Add non-zero optional value. |
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(TBR): Likewise. |
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(SXL): Likewise. |
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(insert_fxm): Handle new default operand value. |
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(extract_fxm): Likewise. |
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(insert_tbr): Likewise. |
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(extract_tbr): Likewise. |
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gas/ |
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* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value. |
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Allow for optional operands without insert functions. |
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gas/testsuite/ |
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* gas/ppc/power8.d: Fixup rfebb test results. |
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* gas/ppc/a2.s: Fix invalid mfcr test. |
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* gas/ppc/a2.d: Likewise. |
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### a/include/opcode/ChangeLog |
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### b/include/opcode/ChangeLog |
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## -1,3 +1,8 @@ |
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+2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
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+ |
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+ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. |
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+ (ppc_optional_operand_value): New inline function. |
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+ |
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2015-06-04 Matthew Wahab <matthew.wahab@arm.com> |
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* aarch64.h (AARCH64_V8_1): New. |
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--- a/include/opcode/ppc.h |
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+++ b/include/opcode/ppc.h |
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@@ -380,6 +380,11 @@ extern const unsigned int num_powerpc_operands; |
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/* This is a CR FIELD that does not use symbolic names. */ |
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#define PPC_OPERAND_CR_REG (0x200000) |
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+ |
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+/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
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+ is omitted, then the value it should use for the operand is stored |
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+ in the SHIFT field of the immediatly following operand field. */ |
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+#define PPC_OPERAND_OPTIONAL_VALUE (0x400000) |
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/* The POWER and PowerPC assemblers use a few macros. We keep them |
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with the operands table for simplicity. The macro table is an |
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@@ -409,4 +414,12 @@ extern const int powerpc_num_macros; |
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extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
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+static inline long |
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+ppc_optional_operand_value (const struct powerpc_operand *operand) |
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+{ |
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+ if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) |
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+ return (operand+1)->shift; |
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+ return 0; |
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+} |
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+ |
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#endif /* PPC_H */ |
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### a/opcodes/ChangeLog |
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### b/opcodes/ChangeLog |
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## -1,3 +1,14 @@ |
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+2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
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+ |
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+ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
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+ * ppc-opc.c (FXM4): Add non-zero optional value. |
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+ (TBR): Likewise. |
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+ (SXL): Likewise. |
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+ (insert_fxm): Handle new default operand value. |
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+ (extract_fxm): Likewise. |
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+ (insert_tbr): Likewise. |
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+ (extract_tbr): Likewise. |
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+ |
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2015-06-16 Matthew Wahab <matthew.wahab@arm.com> |
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* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". |
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--- a/opcodes/ppc-dis.c |
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+++ b/opcodes/ppc-dis.c |
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@@ -452,7 +452,8 @@ skip_optional_operands (const unsigned char *opindex, |
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operand = &powerpc_operands[*opindex]; |
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if ((operand->flags & PPC_OPERAND_NEXT) != 0 |
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|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
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- && operand_value_powerpc (operand, insn, dialect) != 0)) |
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+ && operand_value_powerpc (operand, insn, dialect) != |
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+ ppc_optional_operand_value (operand))) |
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return 0; |
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} |
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--- a/opcodes/ppc-opc.c |
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+++ b/opcodes/ppc-opc.c |
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@@ -382,10 +382,12 @@ const struct powerpc_operand powerpc_operands[] = |
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/* Power4 version for mfcr. */ |
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#define FXM4 FXM + 1 |
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- { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
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+ { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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+ /* If the FXM4 operand is ommitted, use the sentinel value -1. */ |
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+ { -1, -1, NULL, NULL, 0}, |
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/* The IMM20 field in an LI instruction. */ |
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-#define IMM20 FXM4 + 1 |
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+#define IMM20 FXM4 + 2 |
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{ 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
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/* The L field in a D or X form instruction. */ |
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@@ -642,10 +644,12 @@ const struct powerpc_operand powerpc_operands[] = |
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/* The TBR field in an XFX form instruction. This is like the SPR |
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field, but it is optional. */ |
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#define TBR SV + 1 |
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- { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
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+ { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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+ /* If the TBR operand is ommitted, use the value 268. */ |
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+ { -1, 268, NULL, NULL, 0}, |
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/* The TO field in a D or X form instruction. */ |
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-#define TO TBR + 1 |
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+#define TO TBR + 2 |
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#define DUI TO |
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#define TO_MASK (0x1f << 21) |
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{ 0x1f, 21, NULL, NULL, 0 }, |
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@@ -766,10 +770,12 @@ const struct powerpc_operand powerpc_operands[] = |
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/* The S field in a XL form instruction. */ |
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#define SXL S + 1 |
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- { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
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+ { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
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+ /* If the SXL operand is ommitted, use the value 1. */ |
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+ { -1, 1, NULL, NULL, 0}, |
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/* SH field starting at bit position 16. */ |
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-#define SH16 SXL + 1 |
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+#define SH16 SXL + 2 |
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/* The DCM and DGM fields in a Z form instruction. */ |
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#define DCM SH16 |
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#define DGM DCM |
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@@ -1284,19 +1290,13 @@ insert_fxm (unsigned long insn, |
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} |
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} |
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- /* If the optional field on mfcr is missing that means we want to use |
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- the old form of the instruction that moves the whole cr. In that |
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- case we'll have VALUE zero. There doesn't seem to be a way to |
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- distinguish this from the case where someone writes mfcr %r3,0. */ |
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- else if (value == 0) |
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- ; |
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- |
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/* If only one bit of the FXM field is set, we can use the new form |
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of the instruction, which is faster. Unlike the Power4 branch hint |
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encoding, this is not backward compatible. Do not generate the |
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new form unless -mpower4 has been given, or -many and the two |
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operand form of mfcr was used. */ |
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- else if ((value & -value) == value |
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+ else if (value > 0 |
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+ && (value & -value) == value |
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&& ((dialect & PPC_OPCODE_POWER4) != 0 |
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|| ((dialect & PPC_OPCODE_ANY) != 0 |
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&& (insn & (0x3ff << 1)) == 19 << 1))) |
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@@ -1305,7 +1305,10 @@ insert_fxm (unsigned long insn, |
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/* Any other value on mfcr is an error. */ |
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else if ((insn & (0x3ff << 1)) == 19 << 1) |
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{ |
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- *errmsg = _("ignoring invalid mfcr mask"); |
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+ /* A value of -1 means we used the one operand form of |
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+ mfcr which is valid. */ |
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+ if (value != -1) |
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+ *errmsg = _("ignoring invalid mfcr mask"); |
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value = 0; |
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} |
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@@ -1332,6 +1335,8 @@ extract_fxm (unsigned long insn, |
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{ |
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if (mask != 0) |
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*invalid = 1; |
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+ else |
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+ mask = -1; |
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} |
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return mask; |
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@@ -1868,12 +1873,7 @@ extract_sprg (unsigned long insn, |
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} |
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/* The TBR field in an XFX instruction. This is just like SPR, but it |
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- is optional. When TBR is omitted, it must be inserted as 268 (the |
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- magic number of the TB register). These functions treat 0 |
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- (indicating an omitted optional operand) as 268. This means that |
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- ``mftb 4,0'' is not handled correctly. This does not matter very |
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- much, since the architecture manual does not define mftb as |
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- accepting any values other than 268 or 269. */ |
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+ is optional. */ |
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static unsigned long |
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insert_tbr (unsigned long insn, |
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@@ -1881,8 +1881,6 @@ insert_tbr (unsigned long insn, |
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ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
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const char **errmsg) |
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{ |
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- if (value == 0) |
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- value = 268; |
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if (value != 268 && value != 269) |
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*errmsg = _("invalid tbr number"); |
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return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
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@@ -1898,8 +1896,6 @@ extract_tbr (unsigned long insn, |
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ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
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if (ret != 268 && ret != 269) |
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*invalid = 1; |
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- if (ret == 268) |
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- ret = 0; |
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return ret; |
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} |
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