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81 lines
3.0 KiB
81 lines
3.0 KiB
commit 4bc0608a8b693f033555aa5705fdd5fc44cb9a9a |
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Author: Peter Bergner <bergner@vnet.ibm.com> |
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Date: Thu May 14 20:57:50 2015 -0500 |
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Fix some PPC assembler errors. |
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Remove the wait instructions for server processors, since they were never |
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implemented. Also add the extra operands added to the tlbie and slbia |
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instructions with ISA 2.06 and ISA 2.05 respectively. |
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binutils/ |
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* MAINTAINERS: Add myself as PPC maintainer. |
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opcodes/ |
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* ppc-opc.c (IH) New define. |
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(powerpc_opcodes) <wait>: Do not enable for POWER7. |
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<tlbie>: Add RS operand for POWER7. |
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<slbia>: Add IH operand for POWER6. |
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gas/testsuite/ |
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* gas/ppc/power4.d: Add a slbia test. |
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* gas/ppc/power4.s: Likewise. |
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* gas/ppc/power6.d: Add slbia and tlbie tests. |
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* gas/ppc/power6.s: Likewise. |
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* gas/ppc/power7.d: Remove wait tests. Add a tlbie test. |
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* gas/ppc/power7.s: Likewise. |
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### a/opcodes/ChangeLog |
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### b/opcodes/ChangeLog |
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## -1,3 +1,10 @@ |
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+2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
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+ |
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+ * ppc-opc.c (IH) New define. |
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+ (powerpc_opcodes) <wait>: Do not enable for POWER7. |
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+ <tlbie>: Add RS operand for POWER7. |
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+ <slbia>: Add IH operand for POWER6. |
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+ |
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2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
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* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit |
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--- a/opcodes/ppc-opc.c |
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+++ b/opcodes/ppc-opc.c |
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@@ -866,6 +866,9 @@ const struct powerpc_operand powerpc_operands[] = |
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#define ERAT_T UIM + 1 |
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{ 0x7, 21, NULL, NULL, 0 }, |
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+ |
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+#define IH ERAT_T + 1 |
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+ { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
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}; |
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const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
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@@ -4486,7 +4489,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, |
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{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, |
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-{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}}, |
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+{"wait", X(31,62), XWC_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {WC}}, |
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{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, |
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@@ -4780,7 +4783,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}}, |
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-{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}}, |
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+{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}}, |
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+{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER7|TITAN, {RB, L}}, |
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{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, |
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{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}}, |
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@@ -5372,7 +5376,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
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-{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, |
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+{"slbia", X(31,498), 0xff1fffff, POWER6, PPCNONE, {IH}}, |
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+{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, |
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{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}}, |
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