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83 lines
2.8 KiB
83 lines
2.8 KiB
commit 2702856bf45c82cf8e69f2064f5aa15c0ceb6359 |
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Author: Andrew Senkevich <andrew.senkevich@intel.com> |
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Date: Mon Dec 19 13:20:31 2016 +0300 |
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Disable TSX on some Haswell processors. |
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Patch disables Intel TSX on some Haswell processors to avoid TSX |
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on kernels that weren't updated with the latest microcode package |
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(which disables broken feature by default). |
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* sysdeps/x86/cpu-features.c (get_common_indeces): Add |
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stepping identification. |
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(init_cpu_features): Add handle of Haswell. |
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Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.c |
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=================================================================== |
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--- glibc-2.17-c758a686.orig/sysdeps/x86/cpu-features.c |
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+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.c |
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@@ -21,7 +21,8 @@ |
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static inline void |
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get_common_indeces (struct cpu_features *cpu_features, |
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- unsigned int *family, unsigned int *model) |
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+ unsigned int *family, unsigned int *model, |
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+ unsigned int *stepping) |
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{ |
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unsigned int eax; |
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__cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx, |
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@@ -30,6 +31,7 @@ get_common_indeces (struct cpu_features |
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GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].eax = eax; |
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*family = (eax >> 8) & 0x0f; |
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*model = (eax >> 4) & 0x0f; |
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+ *stepping = eax & 0x0f; |
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} |
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static inline void |
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@@ -45,9 +47,11 @@ init_cpu_features (struct cpu_features * |
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/* This spells out "GenuineIntel". */ |
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) |
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{ |
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+ unsigned int stepping; |
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+ |
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kind = arch_kind_intel; |
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- get_common_indeces (cpu_features, &family, &model); |
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+ get_common_indeces (cpu_features, &family, &model, &stepping); |
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/* Intel processors prefer SSE instruction for memory/string |
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routines if they are available. */ |
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@@ -128,6 +132,20 @@ init_cpu_features (struct cpu_features * |
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| bit_Fast_Unaligned_Load |
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| bit_Prefer_PMINUB_for_stringop); |
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break; |
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+ |
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+ case 0x3f: |
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+ /* Xeon E7 v3 with stepping >= 4 has working TSX. */ |
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+ if (stepping >= 4) |
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+ break; |
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+ case 0x3c: |
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+ case 0x45: |
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+ case 0x46: |
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+ /* Disable Intel TSX on Haswell processors (except Xeon E7 v3 |
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+ with stepping >= 4) to avoid TSX on kernels that weren't |
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+ updated with the latest microcode package (which disables |
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+ broken feature by default). */ |
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+ cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM); |
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+ break; |
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} |
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} |
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@@ -148,9 +166,11 @@ init_cpu_features (struct cpu_features * |
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/* This spells out "AuthenticAMD". */ |
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) |
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{ |
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+ unsigned int stepping; |
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+ |
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kind = arch_kind_amd; |
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- get_common_indeces (cpu_features, &family, &model); |
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+ get_common_indeces (cpu_features, &family, &model, &stepping); |
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ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx; |
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