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143 lines
6.6 KiB
143 lines
6.6 KiB
Backport of this upstream commit, with ports/ readded to the path. |
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commit 2b1d7148e3664eeb177ae2fc91bf282d75da7623 |
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Author: Szabolcs Nagy <nsz@port70.net> |
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Date: Mon Jul 6 12:46:43 2015 +0100 |
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[AArch64] make setcontext etc functions consistent with the kernel |
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since |
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https://sourceware.org/ml/libc-alpha/2014-04/msg00006.html |
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setcontext etc is no longer tied to the kernel use of ucontext. |
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in that patch the ucontext reserved space is not used consistently |
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with the kernel abi: the d8,d9 pair is saved in the slot of q8. |
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this is ok (*context functions work together), but probably not |
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desirable (ucontexts created by the kernel and getcontext are |
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subtly different). |
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the fix just replaces dN with qN in the save/restore code, which |
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does a bit more than needed (saves/restores the top half of qN that |
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is not callee saved), but this should not be an issue (and avoids |
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having to deal with endianness). |
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(kernel fpsimd context layout: the first 64bit contains 0x210 the fpsimd |
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context size and 0x46508001 the FPSIMD_MAGIC, the second 64bit is for |
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fpsr and fpcr, and the rest is the 128bit q0..q31 registers). |
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given d8=8.1, d9=9.1,... d15=15.1, the context created by getcontext is |
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current: |
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(gdb) x/40xg ctx.uc_mcontext.__reserved |
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0x410df0 <ctx+464>: 0x0000021046508001 0x0000000000000000 |
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0x410e00 <ctx+480>: 0x0000000000000000 0x0000000000000000 |
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0x410e10 <ctx+496>: 0x0000000000000000 0x0000000000000000 |
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0x410e20 <ctx+512>: 0x0000000000000000 0x0000000000000000 |
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0x410e30 <ctx+528>: 0x0000000000000000 0x0000000000000000 |
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0x410e40 <ctx+544>: 0x0000000000000000 0x0000000000000000 |
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0x410e50 <ctx+560>: 0x0000000000000000 0x0000000000000000 |
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0x410e60 <ctx+576>: 0x0000000000000000 0x0000000000000000 |
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0x410e70 <ctx+592>: 0x0000000000000000 0x0000000000000000 |
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0x410e80 <ctx+608>: 0x4020333333333333 0x4022333333333333 |
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0x410e90 <ctx+624>: 0x0000000000000000 0x0000000000000000 |
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0x410ea0 <ctx+640>: 0x4024333333333333 0x4026333333333333 |
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0x410eb0 <ctx+656>: 0x0000000000000000 0x0000000000000000 |
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0x410ec0 <ctx+672>: 0x4028333333333333 0x402a333333333333 |
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0x410ed0 <ctx+688>: 0x0000000000000000 0x0000000000000000 |
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0x410ee0 <ctx+704>: 0x402c333333333333 0x402e333333333333 |
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0x410ef0 <ctx+720>: 0x0000000000000000 0x0000000000000000 |
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0x410f00 <ctx+736>: 0x0000000000000000 0x0000000000000000 |
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0x410f10 <ctx+752>: 0x0000000000000000 0x0000000000000000 |
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0x410f20 <ctx+768>: 0x0000000000000000 0x0000000000000000 |
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fixed: |
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(gdb) x/40xg ctx.uc_mcontext.__reserved |
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0x410d70 <ctx+464>: 0x0000021046508001 0x0000000000000000 |
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0x410d80 <ctx+480>: 0x0000000000000000 0x0000000000000000 |
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0x410d90 <ctx+496>: 0x0000000000000000 0x0000000000000000 |
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0x410da0 <ctx+512>: 0x0000000000000000 0x0000000000000000 |
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0x410db0 <ctx+528>: 0x0000000000000000 0x0000000000000000 |
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0x410dc0 <ctx+544>: 0x0000000000000000 0x0000000000000000 |
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0x410dd0 <ctx+560>: 0x0000000000000000 0x0000000000000000 |
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0x410de0 <ctx+576>: 0x0000000000000000 0x0000000000000000 |
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0x410df0 <ctx+592>: 0x0000000000000000 0x0000000000000000 |
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0x410e00 <ctx+608>: 0x4020333333333333 0x0000000000000000 |
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0x410e10 <ctx+624>: 0x4022333333333333 0x0000000000000000 |
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0x410e20 <ctx+640>: 0x4024333333333333 0x0000000000000000 |
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0x410e30 <ctx+656>: 0x4026333333333333 0x0000000000000000 |
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0x410e40 <ctx+672>: 0x4028333333333333 0x0000000000000000 |
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0x410e50 <ctx+688>: 0x402a333333333333 0x0000000000000000 |
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0x410e60 <ctx+704>: 0x402c333333333333 0x0000000000000000 |
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0x410e70 <ctx+720>: 0x402e333333333333 0x0000000000000000 |
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0x410e80 <ctx+736>: 0x0000000000000000 0x0000000000000000 |
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0x410e90 <ctx+752>: 0x0000000000000000 0x0000000000000000 |
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0x410ea0 <ctx+768>: 0x0000000000000000 0x0000000000000000 |
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2015-07-06 Szabolcs Nagy <szabolcs.nagy@arm.com> |
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* sysdeps/unix/sysv/linux/aarch64/getcontext.S (__getcontext): Use q |
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registers instead of d ones so the layout is kernel abi compatible. |
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* sysdeps/unix/sysv/linux/aarch64/setcontext.S (__setcontext): Likewise. |
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* sysdeps/unix/sysv/linux/aarch64/swapcontext.S (__swapcontext): |
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Likewise.# Please enter the commit message for your changes. Lines starting |
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diff --git a/ports/sysdeps/unix/sysv/linux/aarch64/getcontext.S b/ports/sysdeps/unix/sysv/linux/aarch64/getcontext.S |
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index adf8037..b72436f 100644 |
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--- a/ports/sysdeps/unix/sysv/linux/aarch64/getcontext.S |
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+++ b/ports/sysdeps/unix/sysv/linux/aarch64/getcontext.S |
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@@ -69,10 +69,10 @@ ENTRY(__getcontext) |
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/* Fill in the FP SIMD context. */ |
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add x3, x2, #oV0 + 8 * SZVREG |
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- stp d8, d9, [x3], # 2 * SZVREG |
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- stp d10, d11, [x3], # 2 * SZVREG |
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- stp d12, d13, [x3], # 2 * SZVREG |
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- stp d14, d15, [x3], # 2 * SZVREG |
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+ stp q8, q9, [x3], # 2 * SZVREG |
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+ stp q10, q11, [x3], # 2 * SZVREG |
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+ stp q12, q13, [x3], # 2 * SZVREG |
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+ stp q14, q15, [x3], # 2 * SZVREG |
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add x3, x2, oFPSR |
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diff --git a/ports/sysdeps/unix/sysv/linux/aarch64/setcontext.S b/ports/sysdeps/unix/sysv/linux/aarch64/setcontext.S |
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index ae67581..8d926f7 100644 |
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--- a/ports/sysdeps/unix/sysv/linux/aarch64/setcontext.S |
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+++ b/ports/sysdeps/unix/sysv/linux/aarch64/setcontext.S |
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@@ -97,10 +97,10 @@ ENTRY (__setcontext) |
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/* Restore the FP SIMD context. */ |
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add x3, x2, #oV0 + 8 * SZVREG |
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- ldp d8, d9, [x3], #2 * SZVREG |
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- ldp d10, d11, [x3], #2 * SZVREG |
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- ldp d12, d13, [x3], #2 * SZVREG |
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- ldp d14, d15, [x3], #2 * SZVREG |
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+ ldp q8, q9, [x3], #2 * SZVREG |
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+ ldp q10, q11, [x3], #2 * SZVREG |
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+ ldp q12, q13, [x3], #2 * SZVREG |
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+ ldp q14, q15, [x3], #2 * SZVREG |
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add x3, x2, oFPSR |
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diff --git a/ports/sysdeps/unix/sysv/linux/aarch64/swapcontext.S b/ports/sysdeps/unix/sysv/linux/aarch64/swapcontext.S |
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index f62fc11..05ad8d3 100644 |
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--- a/ports/sysdeps/unix/sysv/linux/aarch64/swapcontext.S |
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+++ b/ports/sysdeps/unix/sysv/linux/aarch64/swapcontext.S |
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@@ -54,10 +54,10 @@ ENTRY(__swapcontext) |
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/* Fill in the FP SIMD context. */ |
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add x3, x2, #oV0 + 8 * SZVREG |
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- stp d8, d9, [x3], #2 * SZVREG |
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- stp d10, d11, [x3], #2 * SZVREG |
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- stp d12, d13, [x3], #2 * SZVREG |
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- stp d14, d15, [x3], #2 * SZVREG |
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+ stp q8, q9, [x3], #2 * SZVREG |
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+ stp q10, q11, [x3], #2 * SZVREG |
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+ stp q12, q13, [x3], #2 * SZVREG |
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+ stp q14, q15, [x3], #2 * SZVREG |
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add x3, x2, #oFPSR |
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