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172 lines
7.7 KiB
172 lines
7.7 KiB
commit fd486b633e87f8ab2977592d56a6d98168814e2e |
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Author: Peter Bergner <bergner@vnet.ibm.com> |
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Date: Wed Sep 14 22:10:51 2016 -0500 |
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Modify POWER9 support to match final ISA 3.0 documentation. |
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opcodes/ |
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* ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. |
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<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, |
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xor3>: Delete mnemonics. |
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<cp_abort>: Rename mnemonic from ... |
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<cpabort>: ...to this. |
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<setb>: Change to a X form instruction. |
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<sync>: Change to 1 operand form. |
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<copy>: Delete mnemonic. |
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<copy_first>: Rename mnemonic from ... |
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<copy>: ...to this. |
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<paste, paste.>: Delete mnemonics. |
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<paste_last>: Rename mnemonic from ... |
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<paste.>: ...to this. |
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gas/ |
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* testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests. |
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<addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, |
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xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests. |
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<copy, paste.>: Update tests. |
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* testsuite/gas/ppc/power9.s: Likewise. |
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### a/opcodes/ChangeLog |
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### b/opcodes/ChangeLog |
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## -1,3 +1,19 @@ |
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+2016-09-14 Peter Bergner <bergner@vnet.ibm.com> |
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+ |
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+ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. |
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+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, |
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+ xor3>: Delete mnemonics. |
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+ <cp_abort>: Rename mnemonic from ... |
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+ <cpabort>: ...to this. |
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+ <setb>: Change to a X form instruction. |
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+ <sync>: Change to 1 operand form. |
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+ <copy>: Delete mnemonic. |
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+ <copy_first>: Rename mnemonic from ... |
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+ <copy>: ...to this. |
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+ <paste, paste.>: Delete mnemonics. |
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+ <paste_last>: Rename mnemonic from ... |
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+ <paste.>: ...to this. |
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+ |
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2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com> |
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* arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully. |
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--- a/opcodes/ppc-opc.c |
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+++ b/opcodes/ppc-opc.c |
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@@ -3168,7 +3168,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
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{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
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{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
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-{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}}, |
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{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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@@ -3210,8 +3209,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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-{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}}, |
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-{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}}, |
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{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, |
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{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
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@@ -4950,8 +4947,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
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-{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
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-{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}}, |
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+{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
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{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
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@@ -5001,8 +4997,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
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-{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}}, |
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- |
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{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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@@ -5015,7 +5009,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
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{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
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-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
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{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
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{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, |
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@@ -5040,8 +5033,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
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-{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}}, |
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- |
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{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
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{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
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@@ -5080,8 +5071,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
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{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, |
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-{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}}, |
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- |
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{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
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@@ -5548,8 +5537,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
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-{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}}, |
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- |
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{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
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{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, |
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@@ -5916,8 +5903,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, |
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{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
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{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, |
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-{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}}, |
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-{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}}, |
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+{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, |
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+{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, |
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{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, |
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{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, |
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{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, |
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@@ -6085,8 +6072,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
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-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
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-{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}}, |
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+{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
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{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
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{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, |
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@@ -6156,7 +6142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
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-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
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+{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
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{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
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{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
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@@ -6168,6 +6154,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, |
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+{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, |
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{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
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{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
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@@ -6203,9 +6190,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
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{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
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-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}}, |
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-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, |
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-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}}, |
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+{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, |
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{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, |
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{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
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