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187 lines
7.8 KiB
187 lines
7.8 KiB
commit 6fd3a02da5548c71ff469f978444ef6c3af18783 |
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Author: Peter Bergner <bergner@vnet.ibm.com> |
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Date: Wed Jun 22 17:55:17 2016 -0500 |
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Add support for yet some more new ISA 3.0 instructions. |
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opcodes/ |
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* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. |
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(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, |
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mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, |
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xor3>: New mnemonics. |
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<setb>: Change to a VX form instruction. |
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(insert_sh6): Add support for rldixor. |
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(extract_sh6): Likewise. |
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gas/ |
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* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce, |
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mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor, |
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setbool, xor3>: New tests. |
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* testsuite/gas/ppc/power9.s: Likewise. |
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### a/opcodes/ChangeLog |
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### b/opcodes/ChangeLog |
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## -1,3 +1,13 @@ |
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+2016-06-22 Peter Bergner <bergner@vnet.ibm.com> |
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+ |
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+ * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. |
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+ (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, |
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+ mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, |
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+ xor3>: New mnemonics. |
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+ <setb>: Change to a VX form instruction. |
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+ (insert_sh6): Add support for rldixor. |
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+ (extract_sh6): Likewise. |
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+ |
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2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
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* arc-ext.h: Wrap in extern C. |
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--- a/opcodes/ppc-opc.c |
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+++ b/opcodes/ppc-opc.c |
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@@ -238,7 +238,11 @@ const struct powerpc_operand powerpc_operands[] = |
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#define BOE BO + 1 |
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{ 0x1e, 21, insert_boe, extract_boe, 0 }, |
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-#define BH BOE + 1 |
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+ /* The RM field in an X form instruction. */ |
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+#define RM BOE + 1 |
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+ { 0x3, 11, NULL, NULL, 0 }, |
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+ |
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+#define BH RM + 1 |
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{ 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
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/* The BT field in an X or XL form instruction. */ |
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@@ -786,8 +790,9 @@ const struct powerpc_operand powerpc_operands[] = |
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#define EVUIMM_8 EVUIMM_4 + 1 |
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{ 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
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- /* The WS field. */ |
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+ /* The WS or DRM field in an X form instruction. */ |
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#define WS EVUIMM_8 + 1 |
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+#define DRM WS |
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{ 0x7, 11, NULL, NULL, 0 }, |
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/* PowerPC paired singles extensions. */ |
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@@ -2017,7 +2022,11 @@ insert_sh6 (unsigned long insn, |
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ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
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const char **errmsg ATTRIBUTE_UNUSED) |
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{ |
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- return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
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+ /* SH6 operand in the rldixor instructions. */ |
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+ if (PPC_OP (insn) == 4) |
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+ return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); |
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+ else |
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+ return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
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} |
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static long |
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@@ -2025,7 +2034,11 @@ extract_sh6 (unsigned long insn, |
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ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
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int *invalid ATTRIBUTE_UNUSED) |
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{ |
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- return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
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+ /* SH6 operand in the rldixor instructions. */ |
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+ if (PPC_OP (insn) == 4) |
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+ return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); |
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+ else |
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+ return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
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} |
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/* The SPR field in an XFX form instruction. This is flipped--the |
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@@ -2608,6 +2621,9 @@ extract_vleil (unsigned long insn, |
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/* A VX form instruction with a VA tertiary opcode. */ |
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#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) |
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+#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
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+#define VXASH_MASK VXASH (0x3f, 0x1f) |
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+ |
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/* An X form instruction. */ |
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#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
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@@ -2644,6 +2660,9 @@ extract_vleil (unsigned long insn, |
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/* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
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#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) |
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+/* An X form instruction with the RA bits specified as two ops. */ |
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+#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16) |
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+ |
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/* A Z form instruction with the RC bit specified. */ |
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#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) |
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@@ -2696,6 +2715,9 @@ extract_vleil (unsigned long insn, |
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/* An X form wait instruction with everything filled in except the WC field. */ |
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#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
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+/* The mask for an XMMF form instruction. */ |
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+#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) |
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+ |
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/* The mask for a Z form instruction. */ |
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#define Z_MASK ZRC (0x3f, 0x1ff, 1) |
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#define Z2_MASK ZRC (0x3f, 0xff, 1) |
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@@ -3139,6 +3161,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
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{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
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{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
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+{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}}, |
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{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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@@ -3180,6 +3203,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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+{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}}, |
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+{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}}, |
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{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, |
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{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
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{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
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@@ -4918,7 +4943,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
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-{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
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+{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
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+{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}}, |
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{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
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@@ -4968,6 +4994,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
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+{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}}, |
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+ |
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{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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@@ -5005,6 +5033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
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+{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}}, |
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+ |
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{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
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{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
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@@ -5043,6 +5073,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
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{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, |
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+{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}}, |
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+ |
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{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
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{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
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@@ -6914,6 +6946,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
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{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
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{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
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+{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
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+{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, |
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+{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, |
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+{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, |
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+{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, |
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+{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
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+ |
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{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
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{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
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