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213 lines
6.4 KiB
213 lines
6.4 KiB
From 2d656c4ec9d5f68ac39b2a8461b0cd4f77dd7c21 Mon Sep 17 00:00:00 2001 |
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From: Marcin Koss <marcin.koss@intel.com> |
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Date: Thu, 3 Dec 2015 15:19:47 +0100 |
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Subject: [PATCH 3/5] rasdaemon: Add support for Knights Landing processor |
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Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> |
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--- |
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Makefile.am | 3 +- |
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mce-intel-knl.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
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mce-intel.c | 5 +++ |
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ras-mce-handler.c | 1 + |
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ras-mce-handler.h | 1 + |
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5 files changed, 137 insertions(+), 1 deletion(-) |
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create mode 100644 mce-intel-knl.c |
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diff --git a/Makefile.am b/Makefile.am |
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index a6bf18f..a1cb02a 100644 |
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--- a/Makefile.am |
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+++ b/Makefile.am |
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@@ -28,7 +28,8 @@ if WITH_MCE |
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rasdaemon_SOURCES += ras-mce-handler.c mce-intel.c mce-amd-k8.c \ |
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mce-intel-p4-p6.c mce-intel-nehalem.c \ |
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mce-intel-dunnington.c mce-intel-tulsa.c \ |
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- mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c |
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+ mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \ |
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+ mce-intel-knl.c |
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endif |
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if WITH_EXTLOG |
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rasdaemon_SOURCES += ras-extlog-handler.c |
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diff --git a/mce-intel-knl.c b/mce-intel-knl.c |
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new file mode 100644 |
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index 0000000..96b0a59 |
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--- /dev/null |
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+++ b/mce-intel-knl.c |
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@@ -0,0 +1,128 @@ |
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+/* |
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+ * This program is free software; you can redistribute it and/or modify |
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+ * it under the terms of the GNU General Public License as published by |
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+ * the Free Software Foundation; either version 2 of the License, or |
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+ * (at your option) any later version. |
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+ * |
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+ * This program is distributed in the hope that it will be useful, |
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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+ * GNU General Public License for more details. |
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+ * |
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+ * You should have received a copy of the GNU General Public License |
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+ * along with this program; if not, write to the Free Software |
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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+*/ |
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+ |
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+#include <string.h> |
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+#include <stdio.h> |
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+ |
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+#include "ras-mce-handler.h" |
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+#include "bitfield.h" |
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+ |
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+static struct field memctrl_mc7[] = { |
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+ SBITFIELD(16, "CA Parity error"), |
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+ SBITFIELD(17, "Internal Parity error except WDB"), |
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+ SBITFIELD(18, "Internal Parity error from WDB"), |
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+ SBITFIELD(19, "Correctable Patrol Scrub"), |
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+ SBITFIELD(20, "Uncorrectable Patrol Scrub"), |
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+ SBITFIELD(21, "Spare Correctable Error"), |
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+ SBITFIELD(22, "Spare UC Error"), |
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+ SBITFIELD(23, "CORR Chip fail even MC only, 4 bit burst error EDC only"), |
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+ {} |
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+}; |
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+ |
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+void knl_decode_model(struct ras_events *ras, struct mce_event *e) |
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+{ |
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+ uint64_t status = e->status; |
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+ uint32_t mca = status & 0xffff; |
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+ unsigned rank0 = -1, rank1 = -1, chan = 0; |
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+ |
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+ switch (e->bank) { |
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+ case 5: |
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+ switch (EXTRACT(status, 0, 15)) { |
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+ case 0x402: |
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+ mce_snprintf(e->mcastatus_msg, "PCU Internal Errors"); |
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+ break; |
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+ case 0x403: |
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+ mce_snprintf(e->mcastatus_msg, "VCU Internal Errors"); |
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+ break; |
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+ case 0x407: |
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+ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal Errors"); |
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+ break; |
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+ } |
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+ break; |
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+ case 7: case 8: case 9: case 10: |
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+ case 11: case 12: case 13: case 14: |
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+ case 15: case 16: |
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+ if ((EXTRACT(status, 0, 15)) == 0x5) { |
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+ mce_snprintf(e->mcastatus_msg, "Internal Parity error"); |
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+ } else { |
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+ chan = (EXTRACT(status, 0, 3)) + 3 * (e->bank == 15); |
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+ switch (EXTRACT(status, 4, 7)) { |
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+ case 0x0: |
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+ mce_snprintf(e->mcastatus_msg, "Undefined request on channel %d", chan); |
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+ break; |
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+ case 0x1: |
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+ mce_snprintf(e->mcastatus_msg, "Read on channel %d", chan); |
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+ break; |
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+ case 0x2: |
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+ mce_snprintf(e->mcastatus_msg, "Write on channel %d", chan); |
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+ break; |
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+ case 0x3: |
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+ mce_snprintf(e->mcastatus_msg, "CA error on channel %d", chan); |
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+ break; |
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+ case 0x4: |
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+ mce_snprintf(e->mcastatus_msg, "Scrub error on channel %d", chan); |
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+ break; |
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+ } |
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+ } |
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+ decode_bitfield(e, status, memctrl_mc7); |
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+ break; |
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+ default: |
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+ break; |
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+ } |
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+ |
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+ /* |
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+ * Memory error specific code. Returns if the error is not a MC one |
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+ */ |
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+ |
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+ /* Check if the error is at the memory controller */ |
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+ if ((mca >> 7) != 1) |
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+ return; |
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+ |
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+ /* Ignore unless this is an corrected extended error from an iMC bank */ |
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+ if (e->bank < 7 || e->bank > 16 || (status & MCI_STATUS_UC) || |
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+ !test_prefix(7, status & 0xefff)) |
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+ return; |
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+ |
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+ /* |
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+ * Parse the reported channel and ranks |
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+ */ |
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+ |
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+ chan = EXTRACT(status, 0, 3); |
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+ if (chan == 0xf) |
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+ { |
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+ mce_snprintf(e->mc_location, "memory_channel=unspecified"); |
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+ } |
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+ else |
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+ { |
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+ chan = chan + 3 * (e->bank == 15); |
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+ mce_snprintf(e->mc_location, "memory_channel=%d", chan); |
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+ |
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+ if (EXTRACT(e->misc, 62, 62)) |
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+ rank0 = EXTRACT(e->misc, 46, 50); |
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+ if (EXTRACT(e->misc, 63, 63)) |
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+ rank1 = EXTRACT(e->misc, 51, 55); |
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+ |
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+ /* |
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+ * FIXME: The conversion from rank to dimm requires to parse the |
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+ * DMI tables and call failrank2dimm(). |
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+ */ |
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+ if (rank0 != -1 && rank1 != -1) |
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+ mce_snprintf(e->mc_location, "ranks=%d and %d", |
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+ rank0, rank1); |
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+ else if (rank0 != -1) |
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+ mce_snprintf(e->mc_location, "rank=%d", rank0); |
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+ } |
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+} |
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diff --git a/mce-intel.c b/mce-intel.c |
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index 77b929b..032f4e0 100644 |
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--- a/mce-intel.c |
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+++ b/mce-intel.c |
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@@ -397,6 +397,10 @@ int parse_intel_event(struct ras_events *ras, struct mce_event *e) |
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break; |
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case CPU_HASWELL_EPEX: |
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hsw_decode_model(ras, e); |
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+ break; |
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+ case CPU_KNIGHTS_LANDING: |
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+ knl_decode_model(ras, e); |
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+ break; |
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default: |
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break; |
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} |
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@@ -460,6 +464,7 @@ int set_intel_imc_log(enum cputype cputype, unsigned ncpus) |
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case CPU_SANDY_BRIDGE_EP: |
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case CPU_IVY_BRIDGE_EPEX: |
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case CPU_HASWELL_EPEX: |
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+ case CPU_KNIGHTS_LANDING: |
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msr = 0x17f; /* MSR_ERROR_CONTROL */ |
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bit = 0x2; /* MemError Log Enable */ |
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break; |
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diff --git a/ras-mce-handler.c b/ras-mce-handler.c |
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index 23f2488..3b0b05b 100644 |
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--- a/ras-mce-handler.c |
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+++ b/ras-mce-handler.c |
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@@ -223,6 +223,7 @@ int register_mce_handler(struct ras_events *ras, unsigned ncpus) |
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case CPU_SANDY_BRIDGE_EP: |
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case CPU_IVY_BRIDGE_EPEX: |
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case CPU_HASWELL_EPEX: |
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+ case CPU_KNIGHTS_LANDING: |
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set_intel_imc_log(mce->cputype, ncpus); |
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default: |
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break; |
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diff --git a/ras-mce-handler.h b/ras-mce-handler.h |
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index 13b8f52..5466743 100644 |
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--- a/ras-mce-handler.h |
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+++ b/ras-mce-handler.h |
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@@ -119,6 +119,7 @@ void dunnington_decode_model(struct mce_event *e); |
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void snb_decode_model(struct ras_events *ras, struct mce_event *e); |
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void ivb_decode_model(struct ras_events *ras, struct mce_event *e); |
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void hsw_decode_model(struct ras_events *ras, struct mce_event *e); |
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+void knl_decode_model(struct ras_events *ras, struct mce_event *e); |
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void tulsa_decode_model(struct mce_event *e); |
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/* Software defined banks */ |
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-- |
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1.8.3.1 |
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