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55 lines
1.6 KiB
55 lines
1.6 KiB
commit a3d9ab5070b56b49aa91be2887fa5b118012b2cd |
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Author: H.J. Lu <hjl.tools@gmail.com> |
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Date: Tue Mar 31 13:17:51 2015 -0700 |
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Limit threads sharing L2 cache to 2 for SLM/KNL |
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Silvermont and Knights Landing have a modular system design with two cores |
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sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, |
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it should be adjusted for Silvermont and Knights Landing. |
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[BZ #18185] |
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* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads |
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sharing L2 cache to 2 for Silvermont/Knights Landing. |
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diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c |
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index f1cbf50..b99fb9a 100644 |
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--- a/sysdeps/x86_64/cacheinfo.c |
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+++ b/sysdeps/x86_64/cacheinfo.c |
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@@ -585,6 +585,10 @@ init_cacheinfo (void) |
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__cpuid (1, eax, ebx_1, ecx, edx); |
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#endif |
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+ unsigned int family = (eax >> 8) & 0x0f; |
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+ unsigned int model = (eax >> 4) & 0x0f; |
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+ unsigned int extended_model = (eax >> 12) & 0xf0; |
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+ |
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#ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION |
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/* Intel prefers SSSE3 instructions for memory/string routines |
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if they are available. */ |
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@@ -647,6 +651,25 @@ init_cacheinfo (void) |
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} |
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} |
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threads += 1; |
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+ if (threads > 2 && level == 2 && family == 6) |
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+ { |
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+ model += extended_model; |
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+ switch (model) |
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+ { |
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+ case 0x57: |
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+ /* Knights Landing has L2 cache shared by 2 cores. */ |
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+ case 0x37: |
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+ case 0x4a: |
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+ case 0x4d: |
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+ case 0x5a: |
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+ case 0x5d: |
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+ /* Silvermont has L2 cache shared by 2 cores. */ |
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+ threads = 2; |
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+ break; |
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+ default: |
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+ break; |
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+ } |
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+ } |
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} |
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else |
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{
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