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41 lines
1.7 KiB
41 lines
1.7 KiB
commit c3d8dc45c9df199b8334599a6cbd98c9950dba62 |
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Author: Adhemerval Zanella <adhemerval.zanella@linaro.org> |
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Date: Thu Oct 11 15:18:40 2018 -0300 |
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x86: Fix Haswell strong flags (BZ#23709) |
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Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the |
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default flags for Haswell models. Previously, new models were handled by the |
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default switch path, which assumed a Core i3/i5/i7 if AVX is available. After |
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the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags |
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Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and |
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Prefer_PMINUB_for_stringop (only the TSX one). |
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This patch fixes it by disentangle the TSX flag handling from the memory |
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optimization ones. The strstr case cited on patch now selects the |
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__strstr_sse2_unaligned as expected for the Haswell cpu. |
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Checked on x86_64-linux-gnu. |
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[BZ #23709] |
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* sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits |
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independently of other flags. |
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c |
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index 0667e486959a8a91..d134ef3a92cbc83d 100644 |
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--- a/sysdeps/x86/cpu-features.c |
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+++ b/sysdeps/x86/cpu-features.c |
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@@ -133,7 +133,13 @@ init_cpu_features (struct cpu_features *cpu_features) |
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| bit_Fast_Unaligned_Load |
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| bit_Prefer_PMINUB_for_stringop); |
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break; |
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+ } |
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+ /* Disable TSX on some Haswell processors to avoid TSX on kernels that |
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+ weren't updated with the latest microcode package (which disables |
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+ broken feature by default). */ |
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+ switch (model) |
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+ { |
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case 0x3f: |
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/* Xeon E7 v3 with stepping >= 4 has working TSX. */ |
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if (stepping >= 4)
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