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81 lines
2.0 KiB
81 lines
2.0 KiB
commit c95b3011018893fcc473279768a67a24a73bbef2 |
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Author: Wilco <wdijkstr@arm.com> |
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Date: Mon Jun 2 12:20:17 2014 +0100 |
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[AArch64] Rewrite feupdateenv (BZ 17009). |
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diff --git a/ports/sysdeps/aarch64/fpu/feupdateenv.c b/ports/sysdeps/aarch64/fpu/feupdateenv.c |
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index 6d64a9b..ac2f6fe 100644 |
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--- a/ports/sysdeps/aarch64/fpu/feupdateenv.c |
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+++ b/ports/sysdeps/aarch64/fpu/feupdateenv.c |
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@@ -22,16 +22,65 @@ |
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int |
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feupdateenv (const fenv_t *envp) |
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{ |
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+ fpu_control_t fpcr; |
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+ fpu_control_t fpcr_new; |
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+ fpu_control_t updated_fpcr; |
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fpu_fpsr_t fpsr; |
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+ fpu_fpsr_t fpsr_new; |
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+ int excepts; |
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- /* Get the current exception state. */ |
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+ _FPU_GETCW (fpcr); |
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_FPU_GETFPSR (fpsr); |
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+ excepts = fpsr & FE_ALL_EXCEPT; |
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- /* Install new environment. */ |
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- fesetenv (envp); |
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+ if ((envp != FE_DFL_ENV) && (envp != FE_NOMASK_ENV)) |
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+ { |
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+ fpcr_new = envp->__fpcr; |
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+ fpsr_new = envp->__fpsr | excepts; |
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- /* Raise the saved exceptions. */ |
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- feraiseexcept (fpsr & FE_ALL_EXCEPT); |
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+ if (fpcr != fpcr_new) |
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+ _FPU_SETCW (fpcr_new); |
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+ |
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+ if (fpsr != fpsr_new) |
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+ _FPU_SETFPSR (fpsr_new); |
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+ |
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+ if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT)) |
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+ return feraiseexcept (excepts); |
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+ |
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+ return 0; |
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+ } |
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+ |
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+ fpcr_new = fpcr & _FPU_RESERVED; |
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+ fpsr_new = fpsr & (_FPU_FPSR_RESERVED | FE_ALL_EXCEPT); |
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+ |
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+ if (envp == FE_DFL_ENV) |
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+ { |
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+ fpcr_new |= _FPU_DEFAULT; |
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+ fpsr_new |= _FPU_FPSR_DEFAULT; |
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+ } |
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+ else |
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+ { |
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+ fpcr_new |= _FPU_FPCR_IEEE; |
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+ fpsr_new |= _FPU_FPSR_IEEE; |
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+ } |
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+ |
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+ _FPU_SETFPSR (fpsr_new); |
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+ |
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+ if (fpcr != fpcr_new) |
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+ { |
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+ _FPU_SETCW (fpcr_new); |
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+ |
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+ /* Trapping exceptions are optional in AArch64; the relevant enable |
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+ bits in FPCR are RES0 hence the absence of support can be detected |
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+ by reading back the FPCR and comparing with the required value. */ |
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+ _FPU_GETCW (updated_fpcr); |
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+ |
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+ if (fpcr_new & ~updated_fpcr) |
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+ return 1; |
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+ } |
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+ |
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+ if (excepts & (fpcr_new >> FE_EXCEPT_SHIFT)) |
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+ return feraiseexcept (excepts); |
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return 0; |
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}
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