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kernel update 4.14.62 

- added hpsa module from 4.17.14 to enable HP Smart Array to work as
normal scsi device

Signed-off-by: basebuilder_pel7x64builder0 <basebuilder@powerel.org>
master
basebuilder_pel7x64builder0 2018-08-15 12:17:20 +02:00
parent 206347859a
commit cc41c83847
4 changed files with 416 additions and 281 deletions
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602
SOURCES/kernel-4.14-hpsa.c
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File diff suppressed because it is too large Load Diff

90
SOURCES/kernel-4.14-hpsa.h
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@ -57,7 +57,7 @@ struct hpsa_sas_phy {
bool added_to_port; bool added_to_port;
}; };


#define EXTERNAL_QD 7 #define EXTERNAL_QD 7
struct hpsa_scsi_dev_t { struct hpsa_scsi_dev_t {
unsigned int devtype; unsigned int devtype;
int bus, target, lun; /* as presented to the OS */ int bus, target, lun; /* as presented to the OS */
@ -158,6 +158,7 @@ struct bmic_controller_parameters {
#pragma pack() #pragma pack()


struct ctlr_info { struct ctlr_info {
unsigned int *reply_map;
int ctlr; int ctlr;
char devname[8]; char devname[8];
char *product_name; char *product_name;
@ -177,9 +178,7 @@ struct ctlr_info {
# define DOORBELL_INT 1 # define DOORBELL_INT 1
# define SIMPLE_MODE_INT 2 # define SIMPLE_MODE_INT 2
# define MEMQ_MODE_INT 3 # define MEMQ_MODE_INT 3
unsigned int intr[MAX_REPLY_QUEUES]; unsigned int msix_vectors;
unsigned int msix_vector;
unsigned int msi_vector;
int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
struct access_method access; struct access_method access;


@ -295,6 +294,7 @@ struct ctlr_info {
int drv_req_rescan; int drv_req_rescan;
int raid_offload_debug; int raid_offload_debug;
int discovery_polling; int discovery_polling;
int legacy_board;
struct ReportLUNdata *lastlogicals; struct ReportLUNdata *lastlogicals;
int needs_abort_tags_swizzled; int needs_abort_tags_swizzled;
struct workqueue_struct *resubmit_wq; struct workqueue_struct *resubmit_wq;
@ -449,6 +449,23 @@ static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
} }
} }


/*
* Variant of the above; 0x04 turns interrupts off...
*/
static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val)
{
if (val) { /* Turn interrupts on */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else { /* Turn them off */
h->interrupts_enabled = 0;
writel(SA5B_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{ {
if (val) { /* turn on interrupts */ if (val) { /* turn on interrupts */
@ -469,7 +486,7 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
unsigned long register_value = FIFO_EMPTY; unsigned long register_value = FIFO_EMPTY;


/* msi auto clears the interrupt pending bit. */ /* msi auto clears the interrupt pending bit. */
if (unlikely(!(h->msi_vector || h->msix_vector))) { if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {
/* flush the controller write of the reply queue by reading /* flush the controller write of the reply queue by reading
* outbound doorbell status register. * outbound doorbell status register.
*/ */
@ -551,6 +568,14 @@ static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
true : false; true : false;
} }


/*
* Returns true if an interrupt is pending..
*/
static bool SA5B_intr_pending(struct ctlr_info *h)
{
return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING;
}

#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
@ -583,38 +608,53 @@ static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
} }


static struct access_method SA5_access = { static struct access_method SA5_access = {
SA5_submit_command, .submit_command = SA5_submit_command,
SA5_intr_mask, .set_intr_mask = SA5_intr_mask,
SA5_intr_pending, .intr_pending = SA5_intr_pending,
SA5_completed, .command_completed = SA5_completed,
};

/* Duplicate entry of the above to mark unsupported boards */
static struct access_method SA5A_access = {
.submit_command = SA5_submit_command,
.set_intr_mask = SA5_intr_mask,
.intr_pending = SA5_intr_pending,
.command_completed = SA5_completed,
};

static struct access_method SA5B_access = {
.submit_command = SA5_submit_command,
.set_intr_mask = SA5B_intr_mask,
.intr_pending = SA5B_intr_pending,
.command_completed = SA5_completed,
}; };


static struct access_method SA5_ioaccel_mode1_access = { static struct access_method SA5_ioaccel_mode1_access = {
SA5_submit_command, .submit_command = SA5_submit_command,
SA5_performant_intr_mask, .set_intr_mask = SA5_performant_intr_mask,
SA5_ioaccel_mode1_intr_pending, .intr_pending = SA5_ioaccel_mode1_intr_pending,
SA5_ioaccel_mode1_completed, .command_completed = SA5_ioaccel_mode1_completed,
}; };


static struct access_method SA5_ioaccel_mode2_access = { static struct access_method SA5_ioaccel_mode2_access = {
SA5_submit_command_ioaccel2, .submit_command = SA5_submit_command_ioaccel2,
SA5_performant_intr_mask, .set_intr_mask = SA5_performant_intr_mask,
SA5_performant_intr_pending, .intr_pending = SA5_performant_intr_pending,
SA5_performant_completed, .command_completed = SA5_performant_completed,
}; };


static struct access_method SA5_performant_access = { static struct access_method SA5_performant_access = {
SA5_submit_command, .submit_command = SA5_submit_command,
SA5_performant_intr_mask, .set_intr_mask = SA5_performant_intr_mask,
SA5_performant_intr_pending, .intr_pending = SA5_performant_intr_pending,
SA5_performant_completed, .command_completed = SA5_performant_completed,
}; };


static struct access_method SA5_performant_access_no_read = { static struct access_method SA5_performant_access_no_read = {
SA5_submit_command_no_read, .submit_command = SA5_submit_command_no_read,
SA5_performant_intr_mask, .set_intr_mask = SA5_performant_intr_mask,
SA5_performant_intr_pending, .intr_pending = SA5_performant_intr_pending,
SA5_performant_completed, .command_completed = SA5_performant_completed,
}; };


struct board_type { struct board_type {

3
SOURCES/kernel-4.14-hpsa_cmd.h
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@ -142,6 +142,7 @@
#define DOORBELL_CTLR_RESET 0x00000004l #define DOORBELL_CTLR_RESET 0x00000004l
#define DOORBELL_CTLR_RESET2 0x00000020l #define DOORBELL_CTLR_RESET2 0x00000020l
#define DOORBELL_CLEAR_EVENTS 0x00000040l #define DOORBELL_CLEAR_EVENTS 0x00000040l
#define DOORBELL_GENERATE_CHKPT 0x00000080l


#define CFGTBL_Trans_Simple 0x00000002l #define CFGTBL_Trans_Simple 0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l #define CFGTBL_Trans_Performant 0x00000004l
@ -779,6 +780,8 @@ struct bmic_identify_physical_device {
u8 phys_bay_in_box; /* phys drv bay this drive resides */ u8 phys_bay_in_box; /* phys drv bay this drive resides */
__le32 rpm; /* Drive rotational speed in rpm */ __le32 rpm; /* Drive rotational speed in rpm */
u8 device_type; /* type of drive */ u8 device_type; /* type of drive */
#define BMIC_DEVICE_TYPE_CONTROLLER 0x07

u8 sata_version; /* only valid when drive_type is SATA */ u8 sata_version; /* only valid when drive_type is SATA */
__le64 big_total_block_count; __le64 big_total_block_count;
__le64 ris_starting_lba; __le64 ris_starting_lba;

2
SPECS/kernel.spec
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@ -190,11 +190,9 @@ Source1: config-%{version}-%{configarch}
Source4: cpupower.service Source4: cpupower.service
Source5: cpupower.config Source5: cpupower.config
####################################### #######################################
%ifarch x86_64
Source600: kernel-4.14-hpsa.c Source600: kernel-4.14-hpsa.c
Source601: kernel-4.14-hpsa.h Source601: kernel-4.14-hpsa.h
Source602: kernel-4.14-hpsa_cmd.h Source602: kernel-4.14-hpsa_cmd.h
%endif


# Do not package the source tarball. # Do not package the source tarball.
NoSource: 0 NoSource: 0