kernel update 4.14.62
- added hpsa module from 4.17.14 to enable HP Smart Array to work as normal scsi device Signed-off-by: basebuilder_pel7x64builder0 <basebuilder@powerel.org>master
parent
206347859a
commit
cc41c83847
File diff suppressed because it is too large
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@ -57,7 +57,7 @@ struct hpsa_sas_phy {
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bool added_to_port;
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};
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#define EXTERNAL_QD 7
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#define EXTERNAL_QD 7
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struct hpsa_scsi_dev_t {
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unsigned int devtype;
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int bus, target, lun; /* as presented to the OS */
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@ -158,6 +158,7 @@ struct bmic_controller_parameters {
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#pragma pack()
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struct ctlr_info {
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unsigned int *reply_map;
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int ctlr;
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char devname[8];
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char *product_name;
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@ -177,9 +178,7 @@ struct ctlr_info {
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# define DOORBELL_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[MAX_REPLY_QUEUES];
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unsigned int msix_vector;
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unsigned int msi_vector;
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unsigned int msix_vectors;
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int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
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struct access_method access;
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@ -295,6 +294,7 @@ struct ctlr_info {
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int drv_req_rescan;
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int raid_offload_debug;
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int discovery_polling;
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int legacy_board;
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struct ReportLUNdata *lastlogicals;
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int needs_abort_tags_swizzled;
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struct workqueue_struct *resubmit_wq;
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@ -449,6 +449,23 @@ static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
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}
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}
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/*
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* Variant of the above; 0x04 turns interrupts off...
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*/
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static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else { /* Turn them off */
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h->interrupts_enabled = 0;
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writel(SA5B_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* turn on interrupts */
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@ -469,7 +486,7 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
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unsigned long register_value = FIFO_EMPTY;
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/* msi auto clears the interrupt pending bit. */
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if (unlikely(!(h->msi_vector || h->msix_vector))) {
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if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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@ -551,6 +568,14 @@ static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
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true : false;
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}
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/*
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* Returns true if an interrupt is pending..
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*/
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static bool SA5B_intr_pending(struct ctlr_info *h)
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{
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return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING;
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}
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#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
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#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
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#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
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@ -583,38 +608,53 @@ static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
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}
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static struct access_method SA5_access = {
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SA5_submit_command,
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SA5_intr_mask,
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SA5_intr_pending,
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SA5_completed,
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.submit_command = SA5_submit_command,
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.set_intr_mask = SA5_intr_mask,
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.intr_pending = SA5_intr_pending,
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.command_completed = SA5_completed,
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};
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/* Duplicate entry of the above to mark unsupported boards */
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static struct access_method SA5A_access = {
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.submit_command = SA5_submit_command,
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.set_intr_mask = SA5_intr_mask,
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.intr_pending = SA5_intr_pending,
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.command_completed = SA5_completed,
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};
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static struct access_method SA5B_access = {
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.submit_command = SA5_submit_command,
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.set_intr_mask = SA5B_intr_mask,
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.intr_pending = SA5B_intr_pending,
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.command_completed = SA5_completed,
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};
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static struct access_method SA5_ioaccel_mode1_access = {
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SA5_submit_command,
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SA5_performant_intr_mask,
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SA5_ioaccel_mode1_intr_pending,
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SA5_ioaccel_mode1_completed,
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.submit_command = SA5_submit_command,
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.set_intr_mask = SA5_performant_intr_mask,
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.intr_pending = SA5_ioaccel_mode1_intr_pending,
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.command_completed = SA5_ioaccel_mode1_completed,
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};
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static struct access_method SA5_ioaccel_mode2_access = {
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SA5_submit_command_ioaccel2,
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SA5_performant_intr_mask,
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SA5_performant_intr_pending,
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SA5_performant_completed,
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.submit_command = SA5_submit_command_ioaccel2,
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.set_intr_mask = SA5_performant_intr_mask,
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.intr_pending = SA5_performant_intr_pending,
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.command_completed = SA5_performant_completed,
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};
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static struct access_method SA5_performant_access = {
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SA5_submit_command,
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SA5_performant_intr_mask,
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SA5_performant_intr_pending,
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SA5_performant_completed,
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.submit_command = SA5_submit_command,
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.set_intr_mask = SA5_performant_intr_mask,
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.intr_pending = SA5_performant_intr_pending,
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.command_completed = SA5_performant_completed,
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};
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static struct access_method SA5_performant_access_no_read = {
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SA5_submit_command_no_read,
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SA5_performant_intr_mask,
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SA5_performant_intr_pending,
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SA5_performant_completed,
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.submit_command = SA5_submit_command_no_read,
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.set_intr_mask = SA5_performant_intr_mask,
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.intr_pending = SA5_performant_intr_pending,
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.command_completed = SA5_performant_completed,
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};
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struct board_type {
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@ -142,6 +142,7 @@
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#define DOORBELL_CTLR_RESET 0x00000004l
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#define DOORBELL_CTLR_RESET2 0x00000020l
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#define DOORBELL_CLEAR_EVENTS 0x00000040l
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#define DOORBELL_GENERATE_CHKPT 0x00000080l
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#define CFGTBL_Trans_Simple 0x00000002l
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#define CFGTBL_Trans_Performant 0x00000004l
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@ -779,6 +780,8 @@ struct bmic_identify_physical_device {
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u8 phys_bay_in_box; /* phys drv bay this drive resides */
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__le32 rpm; /* Drive rotational speed in rpm */
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u8 device_type; /* type of drive */
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#define BMIC_DEVICE_TYPE_CONTROLLER 0x07
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u8 sata_version; /* only valid when drive_type is SATA */
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__le64 big_total_block_count;
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__le64 ris_starting_lba;
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@ -190,11 +190,9 @@ Source1: config-%{version}-%{configarch}
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Source4: cpupower.service
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Source5: cpupower.config
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#######################################
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%ifarch x86_64
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Source600: kernel-4.14-hpsa.c
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Source601: kernel-4.14-hpsa.h
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Source602: kernel-4.14-hpsa_cmd.h
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%endif
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# Do not package the source tarball.
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NoSource: 0
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