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164 lines
6.4 KiB
164 lines
6.4 KiB
7 years ago
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# commit 9c008155b7d5d1bd81d909497850a2ece28aec50
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# Author: Alan Modra <amodra@gmail.com>
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# Date: Sat Aug 17 18:31:05 2013 +0930
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#
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# PowerPC floating point little-endian [11 of 15]
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# http://sourceware.org/ml/libc-alpha/2013-07/msg00202.html
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#
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# Another little-endian fix.
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#
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# * sysdeps/powerpc/fpu_control.h (_FPU_GETCW): Rewrite using
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# 64-bit int/double union.
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# (_FPU_SETCW): Likewise.
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# * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_GET_DI_FPSCR): Likewise.
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# (_SET_DI_FPSCR, _GET_SI_FPSCR, _SET_SI_FPSCR): Likewise.
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#
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fpu_control.h glibc-2.17-c758a686/sysdeps/powerpc/fpu/fpu_control.h
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fpu_control.h 2014-05-27 22:40:18.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fpu_control.h 2014-05-27 22:43:40.000000000 -0500
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@@ -45,22 +45,26 @@
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#define _FPU_IEEE 0x000000f0
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/* Type of the control word. */
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-typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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+typedef unsigned int fpu_control_t;
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/* Macros for accessing the hardware control word. */
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-#define _FPU_GETCW(__cw) ( { \
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- union { double d; fpu_control_t cw[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
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- (__cw)=tmp.cw[1]; \
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- tmp.cw[1]; } )
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-#define _FPU_SETCW(__cw) { \
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- union { double d; fpu_control_t cw[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- tmp.cw[0] = 0xFFF80000; /* More-or-less arbitrary; this is a QNaN. */ \
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- tmp.cw[1] = __cw; \
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- __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
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-}
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+#define _FPU_GETCW(cw) \
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+ ({union { double __d; unsigned long long __ll; } __u; \
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+ register double __fr; \
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+ __asm__ ("mffs %0" : "=f" (__fr)); \
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+ __u.__d = __fr; \
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+ (cw) = (fpu_control_t) __u.__ll; \
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+ (fpu_control_t) __u.__ll; \
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+ })
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+
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+#define _FPU_SETCW(cw) \
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+ { union { double __d; unsigned long long __ll; } __u; \
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+ register double __fr; \
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+ __u.__ll = 0xfff80000LL << 32; /* This is a QNaN. */ \
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+ __u.__ll |= (cw) & 0xffffffffLL; \
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+ __fr = __u.__d; \
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+ __asm__ ("mtfsf 255,%0" : : "f" (__fr)); \
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+ }
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c 2014-05-27 22:40:18.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c 2014-05-27 22:40:21.000000000 -0500
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@@ -83,7 +83,7 @@
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return 0;
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}
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-typedef unsigned long long di_fpscr_t __attribute__ ((__mode__ (__DI__)));
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+typedef unsigned int di_fpscr_t __attribute__ ((__mode__ (__DI__)));
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typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
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#define _FPSCR_RESERVED 0xfffffff8ffffff04ULL
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@@ -95,50 +95,51 @@
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#define _FPSCR_TEST1_RN 0x0000000000000002ULL
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/* Macros for accessing the hardware control word on Power6[x]. */
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-# define _GET_DI_FPSCR(__fpscr) ({ \
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- union { double d; \
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- di_fpscr_t fpscr; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
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- (__fpscr)=tmp.fpscr; \
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- tmp.fpscr; })
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+#define _GET_DI_FPSCR(__fpscr) \
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+ ({union { double d; di_fpscr_t fpscr; } u; \
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+ register double fr; \
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+ __asm__ ("mffs %0" : "=f" (fr)); \
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+ u.d = fr; \
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+ (__fpscr) = u.fpscr; \
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+ u.fpscr; \
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+ })
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-/* We make sure to zero fp0 after we use it in order to prevent stale data
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+/* We make sure to zero fp after we use it in order to prevent stale data
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in an fp register from making a test-case pass erroneously. */
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-# define _SET_DI_FPSCR(__fpscr) { \
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- union { double d; di_fpscr_t fpscr; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- tmp.fpscr = __fpscr; \
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- /* Set the entire 64-bit FPSCR. */ \
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- __asm__ ("lfd%U0 0,%0; " \
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- ".machine push; " \
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- ".machine \"power6\"; " \
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- "mtfsf 255,0,1,0; " \
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- ".machine pop" : : "m" (tmp.d) : "fr0"); \
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- tmp.d = 0; \
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- __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0"); \
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-}
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-
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-# define _GET_SI_FPSCR(__fpscr) ({ \
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- union { double d; \
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- si_fpscr_t cw[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- __asm__ ("mffs 0; stfd%U0 0,%0" : "=m" (tmp.d) : : "fr0"); \
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- (__fpscr)=tmp.cw[1]; \
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- tmp.cw[0]; })
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+# define _SET_DI_FPSCR(__fpscr) \
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+ { union { double d; di_fpscr_t fpscr; } u; \
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+ register double fr; \
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+ u.fpscr = __fpscr; \
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+ fr = u.d; \
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+ /* Set the entire 64-bit FPSCR. */ \
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+ __asm__ (".machine push; " \
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+ ".machine \"power6\"; " \
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+ "mtfsf 255,%0,1,0; " \
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+ ".machine pop" : : "f" (fr)); \
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+ fr = 0.0; \
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+ }
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+
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+# define _GET_SI_FPSCR(__fpscr) \
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+ ({union { double d; di_fpscr_t fpscr; } u; \
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+ register double fr; \
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+ __asm__ ("mffs %0" : "=f" (fr)); \
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+ u.d = fr; \
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+ (__fpscr) = (si_fpscr_t) u.fpscr; \
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+ (si_fpscr_t) u.fpscr; \
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+ })
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-/* We make sure to zero fp0 after we use it in order to prevent stale data
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+/* We make sure to zero fp after we use it in order to prevent stale data
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in an fp register from making a test-case pass erroneously. */
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-# define _SET_SI_FPSCR(__fpscr) { \
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- union { double d; si_fpscr_t fpscr[2]; } \
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- tmp __attribute__ ((__aligned__(8))); \
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- /* More-or-less arbitrary; this is a QNaN. */ \
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- tmp.fpscr[0] = 0xFFF80000; \
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- tmp.fpscr[1] = __fpscr; \
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- __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0"); \
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- tmp.d = 0; \
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- __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0"); \
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-}
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+# define _SET_SI_FPSCR(__fpscr) \
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+ { union { double d; di_fpscr_t fpscr; } u; \
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+ register double fr; \
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+ /* More-or-less arbitrary; this is a QNaN. */ \
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+ u.fpscr = 0xfff80000ULL << 32; \
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+ u.fpscr |= __fpscr & 0xffffffffULL; \
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+ fr = u.d; \
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+ __asm__ ("mtfsf 255,%0" : : "f" (fr)); \
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+ fr = 0.0; \
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+ }
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void prime_special_regs(int which)
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{
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