base/SOURCES/glibc-rh1027348-1.patch

Backporting the C11 atomic support will allow future algorithms
to be more easily backported to RHEL7. This is initially backported
to support the new semaphore algorithm which is now in RHEL7
(rhbz#1027348).

commit 1ea339b69725cb2f30b5a84cb7ca96111c9a637b
Author: Torvald Riegel <triegel@redhat.com>
Date:   Sat Oct 18 01:02:59 2014 +0200

    Add arch-specific configuration for C11 atomics support.
    
    This sets __HAVE_64B_ATOMICS if provided.  It also sets
    USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the
    __atomic* builtins (aarch64, mips partially) or if this has been
    tested (x86_64); otherwise, this is set to false so that C11 atomics will
    be based on the existing atomic operations.

Index: glibc-2.17-c758a686/ports/sysdeps/aarch64/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/aarch64/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/aarch64/bits/atomic.h
@@ -36,6 +36,8 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 1
 
 /* Compare and exchange.
    For all "bool" routines, we return FALSE if exchange succesful.  */
Index: glibc-2.17-c758a686/ports/sysdeps/alpha/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/alpha/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/alpha/bits/atomic.h
@@ -42,6 +42,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #ifdef UP
 # define __MB		/* nothing */
Index: glibc-2.17-c758a686/ports/sysdeps/arm/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/arm/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/arm/bits/atomic.h
@@ -33,6 +33,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 void __arm_link_error (void);
 
 /* Use the atomic builtins provided by GCC in case the backend provides
Index: glibc-2.17-c758a686/sysdeps/i386/i486/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/i386/i486/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/i386/i486/bits/atomic.h
@@ -54,6 +54,9 @@ typedef uintmax_t uatomic_max_t;
 # endif
 #endif
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   __sync_val_compare_and_swap (mem, oldval, newval)
Index: glibc-2.17-c758a686/ports/sysdeps/ia64/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/ia64/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/ia64/bits/atomic.h
@@ -43,6 +43,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
   (abort (), 0)
Index: glibc-2.17-c758a686/ports/sysdeps/m68k/coldfire/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/m68k/coldfire/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/m68k/coldfire/bits/atomic.h
@@ -49,6 +49,10 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+/* If we have just non-atomic operations, we can as well make them wide.  */
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* The only basic operation needed is compare and exchange.  */
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   ({ __typeof (mem) __gmemp = (mem);				      \
Index: glibc-2.17-c758a686/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/m68k/m680x0/m68020/bits/atomic.h
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   ({ __typeof (*(mem)) __ret;						      \
      __asm __volatile ("cas%.b %0,%2,%1"				      \
Index: glibc-2.17-c758a686/ports/sysdeps/mips/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/mips/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/mips/bits/atomic.h
@@ -43,6 +43,12 @@ typedef uintmax_t uatomic_max_t;
 #define MIPS_PUSH_MIPS2
 #endif
 
+#if _MIPS_SIM == _ABIO32
+#define __HAVE_64B_ATOMICS 0
+#else
+#define __HAVE_64B_ATOMICS 1
+#endif
+
 /* See the comments in <sys/asm.h> about the use of the sync instruction.  */
 #ifndef MIPS_SYNC
 # define MIPS_SYNC	sync
@@ -82,6 +88,8 @@ typedef uintmax_t uatomic_max_t;
 /* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
    support for their efficient implementation was added only in GCC 4.8.  */
 
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+
 /* Compare and exchange.
    For all "bool" routines, we return FALSE if exchange succesful.  */
 
@@ -204,6 +212,8 @@ typedef uintmax_t uatomic_max_t;
 /* This implementation using inline assembly will be removed once glibc
    requires GCC 4.8 or later to build.  */
 
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* Compare and exchange.  For all of the "xxx" routines, we expect a
    "__prev" and a "__cmp" variable to be provided by the enclosing scope,
    in which values are returned.  */
Index: glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/powerpc/powerpc32/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc32/bits/atomic.h
@@ -33,6 +33,9 @@
 # define MUTEX_HINT_REL
 #endif
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /*
  * The 32-bit exchange_bool is different on powerpc64 because the subf
  * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
Index: glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/powerpc/powerpc64/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/powerpc/powerpc64/bits/atomic.h
@@ -33,6 +33,9 @@
 # define MUTEX_HINT_REL
 #endif
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* The 32-bit exchange_bool is different on powerpc64 because the subf
    does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
    (a load word and zero (high 32) form) load.
Index: glibc-2.17-c758a686/sysdeps/s390/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/s390/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/s390/bits/atomic.h
@@ -43,6 +43,8 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
@@ -59,6 +61,7 @@ typedef uintmax_t uatomic_max_t;
      __archold; })
 
 #ifdef __s390x__
+# define __HAVE_64B_ATOMICS 1
 # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
   ({ __typeof (mem) __archmem = (mem);					      \
      __typeof (*mem) __archold = (oldval);				      \
@@ -67,6 +70,7 @@ typedef uintmax_t uatomic_max_t;
 		       : "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" );    \
      __archold; })
 #else
+# define __HAVE_64B_ATOMICS 0
 /* For 31 bit we do not really need 64-bit compare-and-exchange. We can
    implement them by use of the csd instruction. The straightforward
    implementation causes warnings so we skip the definition for now.  */
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc32/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc32/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc32/bits/atomic.h
@@ -47,6 +47,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 /* We have no compare and swap, just test and set.
    The following implementation contends on 64 global locks
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
Index: glibc-2.17-c758a686/sysdeps/sparc/sparc64/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/sparc/sparc64/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/sparc/sparc64/bits/atomic.h
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
Index: glibc-2.17-c758a686/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
+++ glibc-2.17-c758a686/ports/sysdeps/unix/sysv/linux/hppa/bits/atomic.h
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* prev = *addr;
    if (prev == old)
      *addr = new;
Index: glibc-2.17-c758a686/sysdeps/x86_64/bits/atomic.h
===================================================================
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/bits/atomic.h
+++ glibc-2.17-c758a686/sysdeps/x86_64/bits/atomic.h
@@ -55,6 +55,12 @@ typedef uintmax_t uatomic_max_t;
 # endif
 #endif
 
+#define __HAVE_64B_ATOMICS 1
+#if __GNUC_PREREQ (4, 7)
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+#else
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+#endif
 
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   __sync_val_compare_and_swap (mem, oldval, newval)