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64 lines
2.0 KiB
64 lines
2.0 KiB
7 years ago
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---
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mce-intel.c | 3 +++
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ras-mce-handler.c | 5 +++++
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ras-mce-handler.h | 1 +
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3 files changed, 9 insertions(+)
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--- rasdaemon-0.4.1.orig/mce-intel.c 2017-05-30 12:04:54.440167730 -0400
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+++ rasdaemon-0.4.1/mce-intel.c 2017-05-30 12:06:51.705755469 -0400
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@@ -399,6 +399,7 @@ if (test_prefix(11, (e->status & 0xffffL
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hsw_decode_model(ras, e);
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break;
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case CPU_KNIGHTS_LANDING:
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+ case CPU_KNIGHTS_MILL:
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knl_decode_model(ras, e);
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break;
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case CPU_BROADWELL_DE:
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@@ -470,6 +471,8 @@ int set_intel_imc_log(enum cputype cputy
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case CPU_SANDY_BRIDGE_EP:
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case CPU_IVY_BRIDGE_EPEX:
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case CPU_HASWELL_EPEX:
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+ case CPU_KNIGHTS_LANDING:
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+ case CPU_KNIGHTS_MILL:
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msr = 0x17f; /* MSR_ERROR_CONTROL */
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bit = 0x2; /* MemError Log Enable */
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break;
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--- rasdaemon-0.4.1.orig/ras-mce-handler.c 2017-05-30 12:04:54.440167730 -0400
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+++ rasdaemon-0.4.1/ras-mce-handler.c 2017-05-30 12:07:59.850934779 -0400
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@@ -53,6 +53,7 @@ [CPU_XEON75XX] = "Intel Xeon 7500 series
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[CPU_BROADWELL_DE] = "Broadwell DE",
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[CPU_BROADWELL_EPEX] = "Broadwell EP/EX",
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[CPU_KNIGHTS_LANDING] = "Knights Landing",
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+ [CPU_KNIGHTS_MILL] = "Knights Mill",
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};
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static enum cputype select_intel_cputype(struct ras_events *ras)
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@@ -100,6 +101,8 @@ else if (mce->model == 0x3d)
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return CPU_BROADWELL;
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else if (mce->model == 0x57)
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return CPU_KNIGHTS_LANDING;
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+ else if (mce->model == 0x85)
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+ return CPU_KNIGHTS_MILL;
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if (mce->model > 0x1a) {
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log(ALL, LOG_INFO,
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@@ -228,6 +231,8 @@ int register_mce_handler(struct ras_even
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case CPU_SANDY_BRIDGE_EP:
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case CPU_IVY_BRIDGE_EPEX:
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case CPU_HASWELL_EPEX:
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+ case CPU_KNIGHTS_LANDING:
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+ case CPU_KNIGHTS_MILL:
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set_intel_imc_log(mce->cputype, ncpus);
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default:
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break;
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--- rasdaemon-0.4.1.orig/ras-mce-handler.h 2017-05-30 12:04:54.440167730 -0400
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+++ rasdaemon-0.4.1/ras-mce-handler.h 2017-05-30 12:04:58.976113103 -0400
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@@ -48,6 +48,7 @@ enum cputype {
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CPU_BROADWELL_DE,
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CPU_BROADWELL_EPEX,
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CPU_KNIGHTS_LANDING,
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+ CPU_KNIGHTS_MILL,
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};
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struct mce_event {
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