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80 lines
3.5 KiB
80 lines
3.5 KiB
6 years ago
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commit 36f7a9411dcd7dbeb3483bc83a1acbb3dd235deb
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Author: Tom Rix <tom@bumblecow.com>
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Date: Mon Sep 28 12:09:32 2015 +0930
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Patches for illegal ppc 500 instructions
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This change marks a few opcodes as invalid for ppc e500 as well as adds
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a test to verify the change.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,7 @@
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+2015-09-28 Tom Rix <tom@bumblecow.com>
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+
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+ * ppc-opc.c (PPC500): Mark some opcodes as invalid
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+
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2015-09-23 Nick Clifton <nickc@redhat.com>
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* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -4779,7 +4779,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}},
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-{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
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+{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
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{"lqarx", X(31,276), XEH_MASK, POWER8, PPCNONE, {RTQ, RAX, RBX, EH}},
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@@ -4808,10 +4808,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
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{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}},
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-{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER7|TITAN, {RB, L}},
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+{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
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{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
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-{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA0, RB}},
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+{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
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{"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}},
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@@ -4856,7 +4856,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
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{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
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{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
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-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}},
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+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
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{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
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{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
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@@ -5087,7 +5087,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
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{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
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-{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
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+{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
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{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
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{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
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@@ -5145,7 +5145,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
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-{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}},
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+{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
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{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},
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@@ -5197,7 +5197,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
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{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
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{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
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-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}},
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+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
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{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
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{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
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