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54 lines
2.7 KiB
54 lines
2.7 KiB
6 years ago
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commit 6dca4fd141fd0b9fe0ea662295833b8ed43cb4e8
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Author: Anton Blanchard <anton@samba.org>
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Date: Tue Sep 22 15:39:24 2015 +1000
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opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
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opcodes/
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* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
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### a/opcodes/ChangeLog
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### b/opcodes/ChangeLog
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## -1,3 +1,7 @@
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+2015-09-22 Anton Blanchard <anton@samba.org>
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+
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+ * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
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+
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2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-dis.c (print_insn_sparc): Handle the privileged register
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--- a/opcodes/ppc-opc.c
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+++ b/opcodes/ppc-opc.c
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@@ -4878,6 +4878,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}},
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{"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
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{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}},
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+{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, PPCNONE, {RT}},
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{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
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{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
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{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
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@@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
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{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
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{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}},
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+{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, PPCNONE, {RT}},
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{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}},
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{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}},
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{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}},
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@@ -5216,6 +5218,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
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{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
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{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}},
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+{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, PPCNONE, {RS}},
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{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}},
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{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
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{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
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@@ -5242,6 +5245,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}},
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{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}},
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{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}},
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+{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, PPCNONE, {RS}},
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{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}},
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{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}},
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{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}},
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