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base/SOURCES/binutils-2.27-power9.2.patch

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binutils package update Signed-off-by: basebuilder_pel7x64builder0 <basebuilder@powerel.org>
7 years ago
diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.27/gas/config/tc-ppc.c
--- binutils.orig/gas/config/tc-ppc.c 2017-01-17 10:34:39.694867665 +0000
+++ binutils-2.27/gas/config/tc-ppc.c 2017-01-17 10:49:40.367225030 +0000
@@ -2671,7 +2671,8 @@ md_assemble (char *str)
const struct powerpc_operand *operand;
operand = &powerpc_operands[*opindex_ptr];
- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
+ if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
{
unsigned int opcount;
unsigned int num_operands_expected;
@@ -2741,6 +2742,7 @@ md_assemble (char *str)
/* If this is an optional operand, and we are skipping it, just
insert a zero. */
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
&& skip_optional)
{
long val = ppc_optional_operand_value (operand);
@@ -2942,7 +2944,7 @@ md_assemble (char *str)
}
break;
}
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_PPC64_ADDR16_HIGH:
ex.X_add_number = PPC_HI (ex.X_add_number);
@@ -2964,7 +2966,7 @@ md_assemble (char *str)
}
break;
}
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_PPC64_ADDR16_HIGHA:
ex.X_add_number = PPC_HA (ex.X_add_number);
@@ -3087,14 +3089,14 @@ md_assemble (char *str)
{
int tmp_insn = insn & opcode->mask;
- int use_d_reloc = (tmp_insn == E_OR2I_INSN
+ int use_a_reloc = (tmp_insn == E_OR2I_INSN
|| tmp_insn == E_AND2I_DOT_INSN
|| tmp_insn == E_OR2IS_INSN
|| tmp_insn == E_LIS_INSN
|| tmp_insn == E_AND2IS_DOT_INSN);
- int use_a_reloc = (tmp_insn == E_ADD2I_DOT_INSN
+ int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN
|| tmp_insn == E_ADD2IS_INSN
|| tmp_insn == E_CMP16I_INSN
|| tmp_insn == E_MULL2I_INSN
@@ -3377,13 +3379,17 @@ md_assemble (char *str)
however it'll remain clear for dual-mode instructions on
dual-mode and, more importantly, standard-mode processors. */
if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
- ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
+ {
+ ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
+ if (elf_section_data (now_seg) != NULL)
+ elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
+ }
}
#endif
/* Write out the instruction. */
/* Differentiate between two and four byte insns. */
- if (ppc_mach () == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
{
if (PPC_OP_SE_VLE (insn))
insn_length = 2;
@@ -3400,7 +3406,7 @@ md_assemble (char *str)
f = frag_more (insn_length);
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
{
- if (ppc_mach() == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
as_bad (_("instruction address is not a multiple of 2"));
else
as_bad (_("instruction address is not a multiple of 4"));
@@ -6346,7 +6352,7 @@ ppc_frag_check (struct frag *fragP)
if (!fragP->has_code)
return;
- if (ppc_mach() == bfd_mach_ppc_vle)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
{
if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
as_bad (_("instruction address is not a multiple of 2"));
@@ -6367,7 +6373,7 @@ ppc_handle_align (struct frag *fragP)
valueT count = (fragP->fr_next->fr_address
- (fragP->fr_address + fragP->fr_fix));
- if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0)
{
char *dest = fragP->fr_literal + fragP->fr_fix;
@@ -6565,7 +6571,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
}
break;
}
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_PPC_VLE_HI16A:
case BFD_RELOC_PPC_VLE_HI16D:
@@ -6588,7 +6594,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
}
break;
}
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_PPC_VLE_HA16A:
case BFD_RELOC_PPC_VLE_HA16D:
@@ -6730,7 +6736,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
gas_assert (fixP->fx_addsy != NULL);
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_PPC_TLS:
case BFD_RELOC_PPC_TLSGD:
@@ -6854,7 +6860,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
&& !S_IS_DEFINED (fixP->fx_addsy)
&& !S_IS_WEAK (fixP->fx_addsy))
S_SET_WEAK (fixP->fx_addsy);
- /* Fall thru */
+ /* Fallthru */
case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = 0;
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:34:39.823866144 +0000
+++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:55:45.214908333 +0000
@@ -274,8 +274,8 @@ Disassembly of section \.text:
.*: (f3 89 ef 6f|6f ef 89 f3) xvxsigsp vs60,vs61
.*: (7c 06 39 c0|c0 39 06 7c) cmpeqb cr0,r6,r7
.*: (7f 86 39 c0|c0 39 86 7f) cmpeqb cr7,r6,r7
-.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,r8,r9
-.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,r8,r9
+.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,0,r8,r9
+.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,0,r8,r9
.*: (7c 28 49 80|80 49 28 7c) cmprb cr0,1,r8,r9
.*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
.*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
diff -rup binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d
--- binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:34:39.822866157 +0000
+++ binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:53:43.744345513 +0000
@@ -25,148 +25,148 @@ Disassembly of section \.text:
14: R_PPC_VLE_REL15 sub5
18: 70 20 c0 00 e_or2i r1,0
- 18: R_PPC_VLE_LO16D low
+ 18: R_PPC_VLE_LO16A low
1c: 70 40 c0 00 e_or2i r2,0
- 1c: R_PPC_VLE_HI16D high
+ 1c: R_PPC_VLE_HI16A high
20: 70 60 c0 00 e_or2i r3,0
- 20: R_PPC_VLE_HA16D high_adjust
+ 20: R_PPC_VLE_HA16A high_adjust
24: 70 80 c0 00 e_or2i r4,0
- 24: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 24: R_PPC_VLE_SDAREL_LO16A low_sdarel
28: 70 a0 c0 00 e_or2i r5,0
- 28: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 28: R_PPC_VLE_SDAREL_HI16A high_sdarel
2c: 70 40 c0 00 e_or2i r2,0
- 2c: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 2c: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
30: 70 20 c8 00 e_and2i. r1,0
- 30: R_PPC_VLE_LO16D low
+ 30: R_PPC_VLE_LO16A low
34: 70 40 c8 00 e_and2i. r2,0
- 34: R_PPC_VLE_HI16D high
+ 34: R_PPC_VLE_HI16A high
38: 70 60 c8 00 e_and2i. r3,0
- 38: R_PPC_VLE_HA16D high_adjust
+ 38: R_PPC_VLE_HA16A high_adjust
3c: 70 80 c8 00 e_and2i. r4,0
- 3c: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 3c: R_PPC_VLE_SDAREL_LO16A low_sdarel
40: 70 a0 c8 00 e_and2i. r5,0
- 40: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 40: R_PPC_VLE_SDAREL_HI16A high_sdarel
44: 70 40 c8 00 e_and2i. r2,0
- 44: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 44: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
48: 70 40 c8 00 e_and2i. r2,0
- 48: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 48: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
4c: 70 20 d0 00 e_or2is r1,0
- 4c: R_PPC_VLE_LO16D low
+ 4c: R_PPC_VLE_LO16A low
50: 70 40 d0 00 e_or2is r2,0
- 50: R_PPC_VLE_HI16D high
+ 50: R_PPC_VLE_HI16A high
54: 70 60 d0 00 e_or2is r3,0
- 54: R_PPC_VLE_HA16D high_adjust
+ 54: R_PPC_VLE_HA16A high_adjust
58: 70 80 d0 00 e_or2is r4,0
- 58: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 58: R_PPC_VLE_SDAREL_LO16A low_sdarel
5c: 70 a0 d0 00 e_or2is r5,0
- 5c: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 5c: R_PPC_VLE_SDAREL_HI16A high_sdarel
60: 70 40 d0 00 e_or2is r2,0
- 60: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 60: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
64: 70 20 e0 00 e_lis r1,0
- 64: R_PPC_VLE_LO16D low
+ 64: R_PPC_VLE_LO16A low
68: 70 40 e0 00 e_lis r2,0
- 68: R_PPC_VLE_HI16D high
+ 68: R_PPC_VLE_HI16A high
6c: 70 60 e0 00 e_lis r3,0
- 6c: R_PPC_VLE_HA16D high_adjust
+ 6c: R_PPC_VLE_HA16A high_adjust
70: 70 80 e0 00 e_lis r4,0
- 70: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 70: R_PPC_VLE_SDAREL_LO16A low_sdarel
74: 70 a0 e0 00 e_lis r5,0
- 74: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 74: R_PPC_VLE_SDAREL_HI16A high_sdarel
78: 70 40 e0 00 e_lis r2,0
- 78: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 78: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
7c: 70 20 e8 00 e_and2is. r1,0
- 7c: R_PPC_VLE_LO16D low
+ 7c: R_PPC_VLE_LO16A low
80: 70 40 e8 00 e_and2is. r2,0
- 80: R_PPC_VLE_HI16D high
+ 80: R_PPC_VLE_HI16A high
84: 70 60 e8 00 e_and2is. r3,0
- 84: R_PPC_VLE_HA16D high_adjust
+ 84: R_PPC_VLE_HA16A high_adjust
88: 70 80 e8 00 e_and2is. r4,0
- 88: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 88: R_PPC_VLE_SDAREL_LO16A low_sdarel
8c: 70 a0 e8 00 e_and2is. r5,0
- 8c: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 8c: R_PPC_VLE_SDAREL_HI16A high_sdarel
90: 70 40 e8 00 e_and2is. r2,0
- 90: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 90: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
94: 70 01 98 00 e_cmp16i r1,0
- 94: R_PPC_VLE_LO16A low
+ 94: R_PPC_VLE_LO16D low
98: 70 02 98 00 e_cmp16i r2,0
- 98: R_PPC_VLE_HI16A high
+ 98: R_PPC_VLE_HI16D high
9c: 70 03 98 00 e_cmp16i r3,0
- 9c: R_PPC_VLE_HA16A high_adjust
+ 9c: R_PPC_VLE_HA16D high_adjust
a0: 70 04 98 00 e_cmp16i r4,0
- a0: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ a0: R_PPC_VLE_SDAREL_LO16D low_sdarel
a4: 70 05 98 00 e_cmp16i r5,0
- a4: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ a4: R_PPC_VLE_SDAREL_HI16D high_sdarel
a8: 70 02 98 00 e_cmp16i r2,0
- a8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ a8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
ac: 70 01 a8 00 e_cmpl16i r1,0
- ac: R_PPC_VLE_LO16A low
+ ac: R_PPC_VLE_LO16D low
b0: 70 02 a8 00 e_cmpl16i r2,0
- b0: R_PPC_VLE_HI16A high
+ b0: R_PPC_VLE_HI16D high
b4: 70 03 a8 00 e_cmpl16i r3,0
- b4: R_PPC_VLE_HA16A high_adjust
+ b4: R_PPC_VLE_HA16D high_adjust
b8: 70 04 a8 00 e_cmpl16i r4,0
- b8: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ b8: R_PPC_VLE_SDAREL_LO16D low_sdarel
bc: 70 05 a8 00 e_cmpl16i r5,0
- bc: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ bc: R_PPC_VLE_SDAREL_HI16D high_sdarel
c0: 70 02 a8 00 e_cmpl16i r2,0
- c0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ c0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
c4: 70 01 b0 00 e_cmph16i r1,0
- c4: R_PPC_VLE_LO16A low
+ c4: R_PPC_VLE_LO16D low
c8: 70 02 b0 00 e_cmph16i r2,0
- c8: R_PPC_VLE_HI16A high
+ c8: R_PPC_VLE_HI16D high
cc: 70 03 b0 00 e_cmph16i r3,0
- cc: R_PPC_VLE_HA16A high_adjust
+ cc: R_PPC_VLE_HA16D high_adjust
d0: 70 04 b0 00 e_cmph16i r4,0
- d0: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ d0: R_PPC_VLE_SDAREL_LO16D low_sdarel
d4: 70 05 b0 00 e_cmph16i r5,0
- d4: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ d4: R_PPC_VLE_SDAREL_HI16D high_sdarel
d8: 70 02 b0 00 e_cmph16i r2,0
- d8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ d8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
dc: 70 01 b8 00 e_cmphl16i r1,0
- dc: R_PPC_VLE_LO16A low
+ dc: R_PPC_VLE_LO16D low
e0: 70 02 b8 00 e_cmphl16i r2,0
- e0: R_PPC_VLE_HI16A high
+ e0: R_PPC_VLE_HI16D high
e4: 70 03 b8 00 e_cmphl16i r3,0
- e4: R_PPC_VLE_HA16A high_adjust
+ e4: R_PPC_VLE_HA16D high_adjust
e8: 70 04 b8 00 e_cmphl16i r4,0
- e8: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ e8: R_PPC_VLE_SDAREL_LO16D low_sdarel
ec: 70 05 b8 00 e_cmphl16i r5,0
- ec: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ ec: R_PPC_VLE_SDAREL_HI16D high_sdarel
f0: 70 02 b8 00 e_cmphl16i r2,0
- f0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ f0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
f4: 70 01 88 00 e_add2i. r1,0
- f4: R_PPC_VLE_LO16A low
+ f4: R_PPC_VLE_LO16D low
f8: 70 02 88 00 e_add2i. r2,0
- f8: R_PPC_VLE_HI16A high
+ f8: R_PPC_VLE_HI16D high
fc: 70 03 88 00 e_add2i. r3,0
- fc: R_PPC_VLE_HA16A high_adjust
+ fc: R_PPC_VLE_HA16D high_adjust
100: 70 04 88 00 e_add2i. r4,0
- 100: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 100: R_PPC_VLE_SDAREL_LO16D low_sdarel
104: 70 05 88 00 e_add2i. r5,0
- 104: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 104: R_PPC_VLE_SDAREL_HI16D high_sdarel
108: 70 02 88 00 e_add2i. r2,0
- 108: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 108: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
10c: 70 01 90 00 e_add2is r1,0
- 10c: R_PPC_VLE_LO16A low
+ 10c: R_PPC_VLE_LO16D low
110: 70 02 90 00 e_add2is r2,0
- 110: R_PPC_VLE_HI16A high
+ 110: R_PPC_VLE_HI16D high
114: 70 03 90 00 e_add2is r3,0
- 114: R_PPC_VLE_HA16A high_adjust
+ 114: R_PPC_VLE_HA16D high_adjust
118: 70 04 90 00 e_add2is r4,0
- 118: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 118: R_PPC_VLE_SDAREL_LO16D low_sdarel
11c: 70 05 90 00 e_add2is r5,0
- 11c: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 11c: R_PPC_VLE_SDAREL_HI16D high_sdarel
120: 70 02 90 00 e_add2is r2,0
- 120: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 120: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
124: 70 01 a0 00 e_mull2i r1,0
- 124: R_PPC_VLE_LO16A low
+ 124: R_PPC_VLE_LO16D low
128: 70 02 a0 00 e_mull2i r2,0
- 128: R_PPC_VLE_HI16A high
+ 128: R_PPC_VLE_HI16D high
12c: 70 03 a0 00 e_mull2i r3,0
- 12c: R_PPC_VLE_HA16A high_adjust
+ 12c: R_PPC_VLE_HA16D high_adjust
130: 70 04 a0 00 e_mull2i r4,0
- 130: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 130: R_PPC_VLE_SDAREL_LO16D low_sdarel
134: 70 05 a0 00 e_mull2i r5,0
- 134: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 134: R_PPC_VLE_SDAREL_HI16D high_sdarel
138: 70 02 a0 00 e_mull2i r2,0
- 138: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 138: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
diff -rup binutils.orig/include/opcode/ppc.h binutils-2.27/include/opcode/ppc.h
--- binutils.orig/include/opcode/ppc.h 2017-01-17 10:34:39.864865661 +0000
+++ binutils-2.27/include/opcode/ppc.h 2017-01-17 10:49:40.367225030 +0000
@@ -407,6 +407,10 @@ extern const unsigned int num_powerpc_op
is omitted, then the value it should use for the operand is stored
in the SHIFT field of the immediatly following operand field. */
#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
+
+/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
+ only optional when generating 32-bit code. */
+#define PPC_OPERAND_OPTIONAL32 (0x800000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
@@ -444,6 +448,23 @@ ppc_optional_operand_value (const struct
return 0;
}
+/* PowerPC VLE insns. */
+/* Form I16L, uses 16A relocs. */
+#define E_OR2I_INSN 0x7000C000
+#define E_AND2I_DOT_INSN 0x7000C800
+#define E_OR2IS_INSN 0x7000D000
+#define E_LIS_INSN 0x7000E000
+#define E_AND2IS_DOT_INSN 0x7000E800
+
+/* Form I16A, uses 16D relocs. */
+#define E_ADD2I_DOT_INSN 0x70008800
+#define E_ADD2IS_INSN 0x70009000
+#define E_CMP16I_INSN 0x70009800
+#define E_MULL2I_INSN 0x7000A000
+#define E_CMPL16I_INSN 0x7000A800
+#define E_CMPH16I_INSN 0x7000B000
+#define E_CMPHL16I_INSN 0x7000B800
+
#ifdef __cplusplus
}
#endif
diff -rup binutils.orig/opcodes/ppc-dis.c binutils-2.27/opcodes/ppc-dis.c
--- binutils.orig/opcodes/ppc-dis.c 2017-01-17 10:34:40.064863304 +0000
+++ binutils-2.27/opcodes/ppc-dis.c 2017-01-17 10:49:40.391224746 +0000
@@ -236,7 +236,7 @@ get_powerpc_dialect (struct disassemble_
/* Disassemble according to the section headers flags for VLE-mode. */
if (dialect & PPC_OPCODE_VLE
- && info->section->owner != NULL
+ && info->section != NULL && info->section->owner != NULL
&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
--- binutils.orig/opcodes/ppc-opc.c 2017-01-17 10:34:40.064863304 +0000
+++ binutils-2.27/opcodes/ppc-opc.c 2017-01-17 10:49:40.393224722 +0000
@@ -62,10 +62,6 @@ static unsigned long insert_dxdn (unsign
static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
static long extract_fxm (unsigned long, ppc_cpu_t, int *);
-static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
-static long extract_l0 (unsigned long, ppc_cpu_t, int *);
-static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
-static long extract_l1 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
static long extract_li20 (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
@@ -429,20 +425,24 @@ const struct powerpc_operand powerpc_ope
/* The L field in a D or X form instruction. */
#define L IMM20 + 1
+ { 0x1, 21, NULL, NULL, 0 },
+
+ /* The optional L field in tlbie and tlbiel instructions. */
+#define LOPT L + 1
/* The R field in a HTM X form instruction. */
-#define HTM_R L
+#define HTM_R LOPT
{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
- /* The L field in an X form instruction which must be zero. */
-#define L0 L + 1
- { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
-
- /* The L field in an X form instruction which must be one. */
-#define L1 L0 + 1
- { 0x1, 21, insert_l1, extract_l1, 0 },
+ /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
+#define L32OPT LOPT + 1
+ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
+
+ /* The L field in dcbf instruction. */
+#define L2OPT L32OPT + 1
+ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SVC form instruction. */
-#define SVC_LEV L1 + 1
+#define SVC_LEV L2OPT + 1
{ 0x7f, 5, NULL, NULL, 0 },
/* The LEV field in an SC form instruction. */
@@ -688,6 +688,8 @@ const struct powerpc_operand powerpc_ope
#define STRM SR + 1
/* The T field in a tlbilx form instruction. */
#define T STRM
+ /* The L field in wclr instructions. */
+#define L2 STRM
{ 0x3, 21, NULL, NULL, 0 },
/* The ESYNC field in an X (sync) form instruction. */
@@ -1483,58 +1485,6 @@ extract_fxm (unsigned long insn,
return mask;
}
-/* The L field in an X form instruction which must have the value zero. */
-
-static unsigned long
-insert_l0 (unsigned long insn,
- long value,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (value != 0)
- *errmsg = _("invalid operand constant");
- return insn & ~(0x1 << 21);
-}
-
-static long
-extract_l0 (unsigned long insn,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- long value;
-
- value = (insn >> 21) & 0x1;
- if (value != 0)
- *invalid = 1;
- return value;
-}
-
-/* The L field in an X form instruction which must have the value one. */
-
-static unsigned long
-insert_l1 (unsigned long insn,
- long value,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (value != 1)
- *errmsg = _("invalid operand constant");
- return insn | (0x1 << 21);
-}
-
-static long
-extract_l1 (unsigned long insn,
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- long value;
-
- value = (insn >> 21) & 0x1;
- if (value != 1)
- *invalid = 1;
- return value;
-}
-
static unsigned long
insert_li20 (unsigned long insn,
long value,
@@ -3890,12 +3840,12 @@ const struct powerpc_opcode powerpc_opco
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
-{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
+{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
-{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
+{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
@@ -4713,7 +4663,7 @@ const struct powerpc_opcode powerpc_opco
{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
-{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
+{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
@@ -4821,7 +4771,7 @@ const struct powerpc_opcode powerpc_opco
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
-{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
+{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
@@ -4907,7 +4857,7 @@ const struct powerpc_opcode powerpc_opco
{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
-{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
+{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
@@ -5149,7 +5099,7 @@ const struct powerpc_opcode powerpc_opco
{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
-{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
+{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
@@ -6233,8 +6183,8 @@ const struct powerpc_opcode powerpc_opco
{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
-{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
-{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
+{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
+{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},