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64 lines
2.0 KiB

---
mce-intel.c | 3 +++
ras-mce-handler.c | 5 +++++
ras-mce-handler.h | 1 +
3 files changed, 9 insertions(+)
--- rasdaemon-0.4.1.orig/mce-intel.c 2017-05-30 12:04:54.440167730 -0400
+++ rasdaemon-0.4.1/mce-intel.c 2017-05-30 12:06:51.705755469 -0400
@@ -399,6 +399,7 @@ if (test_prefix(11, (e->status & 0xffffL
hsw_decode_model(ras, e);
break;
case CPU_KNIGHTS_LANDING:
+ case CPU_KNIGHTS_MILL:
knl_decode_model(ras, e);
break;
case CPU_BROADWELL_DE:
@@ -470,6 +471,8 @@ int set_intel_imc_log(enum cputype cputy
case CPU_SANDY_BRIDGE_EP:
case CPU_IVY_BRIDGE_EPEX:
case CPU_HASWELL_EPEX:
+ case CPU_KNIGHTS_LANDING:
+ case CPU_KNIGHTS_MILL:
msr = 0x17f; /* MSR_ERROR_CONTROL */
bit = 0x2; /* MemError Log Enable */
break;
--- rasdaemon-0.4.1.orig/ras-mce-handler.c 2017-05-30 12:04:54.440167730 -0400
+++ rasdaemon-0.4.1/ras-mce-handler.c 2017-05-30 12:07:59.850934779 -0400
@@ -53,6 +53,7 @@ [CPU_XEON75XX] = "Intel Xeon 7500 series
[CPU_BROADWELL_DE] = "Broadwell DE",
[CPU_BROADWELL_EPEX] = "Broadwell EP/EX",
[CPU_KNIGHTS_LANDING] = "Knights Landing",
+ [CPU_KNIGHTS_MILL] = "Knights Mill",
};
static enum cputype select_intel_cputype(struct ras_events *ras)
@@ -100,6 +101,8 @@ else if (mce->model == 0x3d)
return CPU_BROADWELL;
else if (mce->model == 0x57)
return CPU_KNIGHTS_LANDING;
+ else if (mce->model == 0x85)
+ return CPU_KNIGHTS_MILL;
if (mce->model > 0x1a) {
log(ALL, LOG_INFO,
@@ -228,6 +231,8 @@ int register_mce_handler(struct ras_even
case CPU_SANDY_BRIDGE_EP:
case CPU_IVY_BRIDGE_EPEX:
case CPU_HASWELL_EPEX:
+ case CPU_KNIGHTS_LANDING:
+ case CPU_KNIGHTS_MILL:
set_intel_imc_log(mce->cputype, ncpus);
default:
break;
--- rasdaemon-0.4.1.orig/ras-mce-handler.h 2017-05-30 12:04:54.440167730 -0400
+++ rasdaemon-0.4.1/ras-mce-handler.h 2017-05-30 12:04:58.976113103 -0400
@@ -48,6 +48,7 @@ enum cputype {
CPU_BROADWELL_DE,
CPU_BROADWELL_EPEX,
CPU_KNIGHTS_LANDING,
+ CPU_KNIGHTS_MILL,
};
struct mce_event {