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284 lines
13 KiB
284 lines
13 KiB
7 years ago
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# commit 4a28b3ca4bc52d9a3ac0d9edb53d3de510e1b77c
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# Author: Anton Blanchard <anton@au1.ibm.com>
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# Date: Sat Aug 17 18:28:55 2013 +0930
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#
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# PowerPC floating point little-endian [8 of 15]
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# http://sourceware.org/ml/libc-alpha/2013-07/msg00199.html
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#
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# Corrects floating-point environment code for little-endian.
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#
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# * sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int
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# array with long long.
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# * sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust.
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# * sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust.
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# * sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust.
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# * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust.
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# * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust.
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# * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust.
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# * sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust.
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# * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust.
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# * sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust.
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# * sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust.
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# * sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust.
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# * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust.
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# * sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust.
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#
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c 2014-05-27 22:31:43.000000000 -0500
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@@ -145,7 +145,7 @@
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feraiseexcept (FE_INVALID_SQRT);
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fenv_union_t u = { .fenv = fegetenv_register () };
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- if ((u.l[1] & FE_INVALID) == 0)
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+ if ((u.l & FE_INVALID) == 0)
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#endif
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feraiseexcept (FE_INVALID);
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x = a_nan.value;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c 2014-05-27 22:31:43.000000000 -0500
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@@ -121,7 +121,7 @@
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feraiseexcept (FE_INVALID_SQRT);
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fenv_union_t u = { .fenv = fegetenv_register () };
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- if ((u.l[1] & FE_INVALID) == 0)
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+ if ((u.l & FE_INVALID) == 0)
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#endif
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feraiseexcept (FE_INVALID);
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x = a_nan.value;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c 2014-05-27 22:31:43.000000000 -0500
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@@ -28,8 +28,8 @@
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u.fenv = fegetenv_register ();
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/* Clear the relevant bits. */
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- u.l[1] = u.l[1] & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID)
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- | (excepts & FPSCR_STICKY_BITS));
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+ u.l = u.l & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID)
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+ | (excepts & FPSCR_STICKY_BITS));
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/* Put the new state in effect. */
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fesetenv_register (u.fenv);
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c 2014-05-27 22:31:43.000000000 -0500
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@@ -32,15 +32,15 @@
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fe.fenv = fegetenv_register ();
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if (excepts & FE_INEXACT)
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- fe.l[1] &= ~(1 << (31 - FPSCR_XE));
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+ fe.l &= ~(1 << (31 - FPSCR_XE));
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if (excepts & FE_DIVBYZERO)
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- fe.l[1] &= ~(1 << (31 - FPSCR_ZE));
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+ fe.l &= ~(1 << (31 - FPSCR_ZE));
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if (excepts & FE_UNDERFLOW)
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- fe.l[1] &= ~(1 << (31 - FPSCR_UE));
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+ fe.l &= ~(1 << (31 - FPSCR_UE));
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if (excepts & FE_OVERFLOW)
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- fe.l[1] &= ~(1 << (31 - FPSCR_OE));
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+ fe.l &= ~(1 << (31 - FPSCR_OE));
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if (excepts & FE_INVALID)
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- fe.l[1] &= ~(1 << (31 - FPSCR_VE));
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+ fe.l &= ~(1 << (31 - FPSCR_VE));
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fesetenv_register (fe.fenv);
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new = __fegetexcept ();
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c 2014-05-27 22:31:43.000000000 -0500
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@@ -32,15 +32,15 @@
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fe.fenv = fegetenv_register ();
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if (excepts & FE_INEXACT)
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- fe.l[1] |= (1 << (31 - FPSCR_XE));
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+ fe.l |= (1 << (31 - FPSCR_XE));
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if (excepts & FE_DIVBYZERO)
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- fe.l[1] |= (1 << (31 - FPSCR_ZE));
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+ fe.l |= (1 << (31 - FPSCR_ZE));
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if (excepts & FE_UNDERFLOW)
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- fe.l[1] |= (1 << (31 - FPSCR_UE));
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+ fe.l |= (1 << (31 - FPSCR_UE));
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if (excepts & FE_OVERFLOW)
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- fe.l[1] |= (1 << (31 - FPSCR_OE));
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+ fe.l |= (1 << (31 - FPSCR_OE));
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if (excepts & FE_INVALID)
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- fe.l[1] |= (1 << (31 - FPSCR_VE));
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+ fe.l |= (1 << (31 - FPSCR_VE));
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fesetenv_register (fe.fenv);
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new = __fegetexcept ();
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c 2014-05-27 22:31:43.000000000 -0500
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@@ -27,15 +27,15 @@
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fe.fenv = fegetenv_register ();
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- if (fe.l[1] & (1 << (31 - FPSCR_XE)))
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+ if (fe.l & (1 << (31 - FPSCR_XE)))
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result |= FE_INEXACT;
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- if (fe.l[1] & (1 << (31 - FPSCR_ZE)))
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+ if (fe.l & (1 << (31 - FPSCR_ZE)))
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result |= FE_DIVBYZERO;
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- if (fe.l[1] & (1 << (31 - FPSCR_UE)))
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+ if (fe.l & (1 << (31 - FPSCR_UE)))
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result |= FE_UNDERFLOW;
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- if (fe.l[1] & (1 << (31 - FPSCR_OE)))
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+ if (fe.l & (1 << (31 - FPSCR_OE)))
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result |= FE_OVERFLOW;
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- if (fe.l[1] & (1 << (31 - FPSCR_VE)))
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+ if (fe.l & (1 << (31 - FPSCR_VE)))
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result |= FE_INVALID;
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return result;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c 2014-05-27 22:33:09.000000000 -0500
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@@ -30,13 +30,12 @@
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/* Clear everything except for the rounding modes and non-IEEE arithmetic
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flag. */
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- new.l[1] = old.l[1] & 7;
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- new.l[0] = old.l[0];
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+ new.l = old.l & 0xffffffff00000007LL;
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/* If the old env had any eabled exceptions, then mask SIGFPE in the
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MSR FE0/FE1 bits. This may allow the FPU to run faster because it
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always takes the default action and can not generate SIGFPE. */
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- if ((old.l[1] & _FPU_MASK_ALL) != 0)
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+ if ((old.l & _FPU_MASK_ALL) != 0)
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(void)__fe_mask_env ();
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/* Put the new state in effect. */
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h 2014-05-27 22:31:43.000000000 -0500
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@@ -69,7 +69,7 @@
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typedef union
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{
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fenv_t fenv;
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- unsigned int l[2];
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+ unsigned long long l;
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} fenv_union_t;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c 2014-05-27 22:35:18.000000000 -0500
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@@ -36,14 +36,14 @@
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exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
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hardware into "precise mode" and may cause the FPU to run slower on some
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hardware. */
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- if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
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+ if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
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(void)__fe_nomask_env ();
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/* If the old env had any enabled exceptions and the new env has no enabled
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exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
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FPU to run faster because it always takes the default action and can not
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generate SIGFPE. */
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- if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
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+ if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
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(void)__fe_mask_env ();
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fesetenv_register (*envp);
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c 2014-05-27 22:34:23.000000000 -0500
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@@ -36,20 +36,20 @@
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/* Restore rounding mode and exception enable from *envp and merge
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exceptions. Leave fraction rounded/inexact and FP result/CC bits
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unchanged. */
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- new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
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+ new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
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/* If the old env has no eabled exceptions and the new env has any enabled
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exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
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the hardware into "precise mode" and may cause the FPU to run slower on
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some hardware. */
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- if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
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+ if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
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(void)__fe_nomask_env ();
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/* If the old env had any eabled exceptions and the new env has no enabled
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exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
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FPU to run faster because it always takes the default action and can not
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generate SIGFPE. */
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- if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
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+ if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
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(void)__fe_mask_env ();
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/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c 2014-05-27 22:31:43.000000000 -0500
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@@ -28,7 +28,7 @@
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u.fenv = fegetenv_register ();
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/* Return (all of) it. */
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- *flagp = u.l[1] & excepts & FE_ALL_EXCEPT;
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+ *flagp = u.l & excepts & FE_ALL_EXCEPT;
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/* Success. */
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return 0;
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diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c
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--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c 2014-05-27 22:31:42.000000000 -0500
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+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c 2014-05-27 22:31:43.000000000 -0500
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@@ -34,11 +34,11 @@
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u.fenv = fegetenv_register ();
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/* Add the exceptions */
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- u.l[1] = (u.l[1]
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- | (excepts & FPSCR_STICKY_BITS)
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- /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */
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- | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
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- & FE_INVALID_SOFTWARE));
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+ u.l = (u.l
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+ | (excepts & FPSCR_STICKY_BITS)
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+ /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */
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+ | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
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+ & FE_INVALID_SOFTWARE));
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/* Store the new status word (along with the rest of the environment),
|
||
|
|
triggering any appropriate exceptions. */
|
||
|
|
@@ -50,7 +50,7 @@
|
||
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|
don't have FE_INVALID_SOFTWARE implemented. Detect this
|
||
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|
case and raise FE_INVALID_SNAN instead. */
|
||
|
|
u.fenv = fegetenv_register ();
|
||
|
|
- if ((u.l[1] & FE_INVALID) == 0)
|
||
|
|
+ if ((u.l & FE_INVALID) == 0)
|
||
|
|
set_fpscr_bit (FPSCR_VXSNAN);
|
||
|
|
}
|
||
|
|
|
||
|
|
diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c
|
||
|
|
--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c 2014-05-27 22:31:42.000000000 -0500
|
||
|
|
+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c 2014-05-27 22:31:43.000000000 -0500
|
||
|
|
@@ -32,10 +32,10 @@
|
||
|
|
flag = *flagp & excepts;
|
||
|
|
|
||
|
|
/* Replace the exception status */
|
||
|
|
- u.l[1] = ((u.l[1] & ~(FPSCR_STICKY_BITS & excepts))
|
||
|
|
- | (flag & FPSCR_STICKY_BITS)
|
||
|
|
- | (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
|
||
|
|
- & FE_INVALID_SOFTWARE));
|
||
|
|
+ u.l = ((u.l & ~(FPSCR_STICKY_BITS & excepts))
|
||
|
|
+ | (flag & FPSCR_STICKY_BITS)
|
||
|
|
+ | (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
|
||
|
|
+ & FE_INVALID_SOFTWARE));
|
||
|
|
|
||
|
|
/* Store the new status word (along with the rest of the environment).
|
||
|
|
This may cause floating-point exceptions if the restored state
|
||
|
|
diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c
|
||
|
|
--- glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c 2014-05-27 22:31:42.000000000 -0500
|
||
|
|
+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c 2014-05-27 22:31:43.000000000 -0500
|
||
|
|
@@ -28,6 +28,6 @@
|
||
|
|
|
||
|
|
/* The FE_INVALID bit is dealt with correctly by the hardware, so we can
|
||
|
|
just: */
|
||
|
|
- return u.l[1] & excepts;
|
||
|
|
+ return u.l & excepts;
|
||
|
|
}
|
||
|
|
libm_hidden_def (fetestexcept)
|