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332 lines
11 KiB
332 lines
11 KiB
/* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* GPL LICENSE SUMMARY |
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* |
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of version 2 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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* The full GNU General Public License is included in this distribution |
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* in the file called LICENSE.GPL. |
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* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name of Intel Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _ISCI_PROBE_ROMS_H_ |
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#define _ISCI_PROBE_ROMS_H_ |
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#ifdef __KERNEL__ |
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#include <linux/firmware.h> |
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#include <linux/pci.h> |
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#include <linux/efi.h> |
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#include "isci.h" |
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#define SCIC_SDS_PARM_NO_SPEED 0 |
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/* generation 1 (i.e. 1.5 Gb/s) */ |
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#define SCIC_SDS_PARM_GEN1_SPEED 1 |
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/* generation 2 (i.e. 3.0 Gb/s) */ |
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#define SCIC_SDS_PARM_GEN2_SPEED 2 |
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/* generation 3 (i.e. 6.0 Gb/s) */ |
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#define SCIC_SDS_PARM_GEN3_SPEED 3 |
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#define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED |
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/* parameters that can be set by module parameters */ |
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struct sci_user_parameters { |
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struct sci_phy_user_params { |
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/** |
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* This field specifies the NOTIFY (ENABLE SPIN UP) primitive |
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* insertion frequency for this phy index. |
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*/ |
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u32 notify_enable_spin_up_insertion_frequency; |
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/** |
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* This method specifies the number of transmitted DWORDs within which |
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* to transmit a single ALIGN primitive. This value applies regardless |
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* of what type of device is attached or connection state. A value of |
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* 0 indicates that no ALIGN primitives will be inserted. |
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*/ |
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u16 align_insertion_frequency; |
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/** |
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* This method specifies the number of transmitted DWORDs within which |
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* to transmit 2 ALIGN primitives. This applies for SAS connections |
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* only. A minimum value of 3 is required for this field. |
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*/ |
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u16 in_connection_align_insertion_frequency; |
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/** |
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* This field indicates the maximum speed generation to be utilized |
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* by phys in the supplied port. |
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* - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s). |
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* - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s). |
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* - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s). |
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*/ |
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u8 max_speed_generation; |
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} phys[SCI_MAX_PHYS]; |
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/** |
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* This field specifies the maximum number of direct attached devices |
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* that can have power supplied to them simultaneously. |
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*/ |
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u8 max_concurr_spinup; |
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/** |
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* This field specifies the number of seconds to allow a phy to consume |
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* power before yielding to another phy. |
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* |
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*/ |
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u8 phy_spin_up_delay_interval; |
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/** |
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* These timer values specifies how long a link will remain open with no |
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* activity in increments of a microsecond, it can be in increments of |
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* 100 microseconds if the upper most bit is set. |
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* |
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*/ |
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u16 stp_inactivity_timeout; |
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u16 ssp_inactivity_timeout; |
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/** |
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* These timer values specifies how long a link will remain open in increments |
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* of 100 microseconds. |
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* |
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*/ |
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u16 stp_max_occupancy_timeout; |
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u16 ssp_max_occupancy_timeout; |
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/** |
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* This timer value specifies how long a link will remain open with no |
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* outbound traffic in increments of a microsecond. |
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* |
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*/ |
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u8 no_outbound_task_timeout; |
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}; |
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#define SCIC_SDS_PARM_PHY_MASK_MIN 0x0 |
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#define SCIC_SDS_PARM_PHY_MASK_MAX 0xF |
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#define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4 |
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struct sci_oem_params; |
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int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version); |
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struct isci_orom; |
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struct isci_orom *isci_request_oprom(struct pci_dev *pdev); |
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enum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem, |
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struct isci_orom *orom, int scu_index); |
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struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw); |
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struct isci_orom *isci_get_efi_var(struct pci_dev *pdev); |
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struct isci_oem_hdr { |
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u8 sig[4]; |
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u8 rev_major; |
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u8 rev_minor; |
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u16 len; |
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u8 checksum; |
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u8 reserved1; |
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u16 reserved2; |
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} __attribute__ ((packed)); |
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#else |
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#define SCI_MAX_PORTS 4 |
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#define SCI_MAX_PHYS 4 |
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#define SCI_MAX_CONTROLLERS 2 |
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#endif |
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#define ISCI_FW_NAME "isci/isci_firmware.bin" |
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#define ROMSIGNATURE 0xaa55 |
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#define ISCI_OEM_SIG "$OEM" |
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#define ISCI_OEM_SIG_SIZE 4 |
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#define ISCI_ROM_SIG "ISCUOEMB" |
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#define ISCI_ROM_SIG_SIZE 8 |
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#define ISCI_EFI_VENDOR_GUID \ |
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EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \ |
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0x1a, 0x04, 0xc6) |
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#define ISCI_EFI_VAR_NAME "RstScuO" |
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#define ISCI_ROM_VER_1_0 0x10 |
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#define ISCI_ROM_VER_1_1 0x11 |
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#define ISCI_ROM_VER_1_3 0x13 |
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#define ISCI_ROM_VER_LATEST ISCI_ROM_VER_1_3 |
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/* Allowed PORT configuration modes APC Automatic PORT configuration mode is |
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* defined by the OEM configuration parameters providing no PHY_MASK parameters |
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* for any PORT. i.e. There are no phys assigned to any of the ports at start. |
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* MPC Manual PORT configuration mode is defined by the OEM configuration |
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* parameters providing a PHY_MASK value for any PORT. It is assumed that any |
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* PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned. |
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* A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs |
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* being assigned is sufficient to declare manual PORT configuration. |
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*/ |
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enum sci_port_configuration_mode { |
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SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0, |
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SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1 |
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}; |
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struct sci_bios_oem_param_block_hdr { |
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uint8_t signature[ISCI_ROM_SIG_SIZE]; |
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uint16_t total_block_length; |
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uint8_t hdr_length; |
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uint8_t version; |
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uint8_t preboot_source; |
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uint8_t num_elements; |
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uint16_t element_length; |
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uint8_t reserved[8]; |
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} __attribute__ ((packed)); |
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struct sci_oem_params { |
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struct { |
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uint8_t mode_type; |
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uint8_t max_concurr_spin_up; |
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/* |
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* This bitfield indicates the OEM's desired default Tx |
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* Spread Spectrum Clocking (SSC) settings for SATA and SAS. |
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* NOTE: Default SSC Modulation Frequency is 31.5KHz. |
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*/ |
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union { |
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struct { |
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/* |
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* NOTE: Max spread for SATA is +0 / -5000 PPM. |
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* Down-spreading SSC (only method allowed for SATA): |
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* SATA SSC Tx Disabled = 0x0 |
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* SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 |
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* SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 |
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* SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 |
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* SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 |
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*/ |
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uint8_t ssc_sata_tx_spread_level:4; |
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/* |
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* SAS SSC Tx Disabled = 0x0 |
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* |
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* NOTE: Max spread for SAS down-spreading +0 / |
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* -2300 PPM |
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* Down-spreading SSC: |
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* SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 |
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* SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 |
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* |
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* NOTE: Max spread for SAS center-spreading +2300 / |
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* -2300 PPM |
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* Center-spreading SSC: |
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* SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 |
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* SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 |
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*/ |
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uint8_t ssc_sas_tx_spread_level:3; |
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/* |
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* NOTE: Refer to the SSC section of the SAS 2.x |
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* Specification for proper setting of this field. |
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* For standard SAS Initiator SAS PHY operation it |
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* should be 0 for Down-spreading. |
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* SAS SSC Tx spread type: |
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* Down-spreading SSC = 0 |
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* Center-spreading SSC = 1 |
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*/ |
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uint8_t ssc_sas_tx_type:1; |
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}; |
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uint8_t do_enable_ssc; |
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}; |
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/* |
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* This field indicates length of the SAS/SATA cable between |
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* host and device. |
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* This field is used make relationship between analog |
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* parameters of the phy in the silicon and length of the cable. |
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* Supported cable attenuation levels: |
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* "short"- up to 3m, "medium"-3m to 6m, and "long"- more than |
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* 6m. |
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* |
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* This is bit mask field: |
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* |
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* BIT: (MSB) 7 6 5 4 |
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* ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable |
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* length assignment |
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* BIT: 3 2 1 0 (LSB) |
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* ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length |
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* assignment |
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* |
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* BITS 7-4 are set when the cable length is assigned to medium |
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* BITS 3-0 are set when the cable length is assigned to long |
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* |
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* The BIT positions are clear when the cable length is |
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* assigned to short. |
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* |
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* Setting the bits for both long and medium cable length is |
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* undefined. |
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* |
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* A value of 0x84 would assign |
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* phy3 - medium |
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* phy2 - long |
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* phy1 - short |
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* phy0 - short |
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*/ |
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uint8_t cable_selection_mask; |
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} controller; |
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struct { |
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uint8_t phy_mask; |
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} ports[SCI_MAX_PORTS]; |
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struct sci_phy_oem_params { |
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struct { |
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uint32_t high; |
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uint32_t low; |
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} sas_address; |
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uint32_t afe_tx_amp_control0; |
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uint32_t afe_tx_amp_control1; |
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uint32_t afe_tx_amp_control2; |
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uint32_t afe_tx_amp_control3; |
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} phys[SCI_MAX_PHYS]; |
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} __attribute__ ((packed)); |
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struct isci_orom { |
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struct sci_bios_oem_param_block_hdr hdr; |
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struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS]; |
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} __attribute__ ((packed)); |
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#endif
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