This versions has the risk of "DMC RAM corruption issue"
fixed on 1.23.
So let's remove old version and let only the latest one available
for now.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Version: 1.23
Date : 10/19/2015
Notes:
Following additions from ver1.22
1. WA for Palette and DMC RAM corruption issue.
DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.22
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
The code points to the major version that is a link to the most
recent one, so we can remove the old firmware blobs.
For tests and validation purposes we will let few minor versions
available, but we need to let linux-firmware repo as
clean as possible, so let's remove old and unused ones.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Version: 1.22
Date : 9/23/2015
Notes:
Following additions from ver1.21
1. PLL lock wait time updated
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.21
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from previous version
1. Updated FW for NV12 enabling
2. Changes to the waits times for pll enable and disable.
3. Fixed GT interrupts issue
4. DC3_DC5_COUNT: 80038
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1:
1. Performance Improvement.
2. Fix reset issue.
3. Scheduler fix.
4. Merge in new power management features.
5. Firmware layout changes.
6. Force Fence WA to guarantee correct ordering of GTT writes from uKernel.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
The code points to the major version that is a link to the most
recent one, so we can remove the old firmware blobs.
For tests and validation purposes we will let at least 3 latest
minor available, but we need to let linux-firmware repo as
clean as possible, so let's remove old and unused ones.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.20
1. Fixed GT interrupts issue when DC6 is enabled
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.20
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.19
1. Changes to the waits times for pll enable and disable.
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.19
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.04
1. No changes to the FW program itself
2. CSS header size field was fixed
3. Date field is fixed in header.
4. DC3_DC5_COUNT � 80038
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions:
1. Updated FW for NV12 enabling
3. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.18 and ver1.17
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions:
1. No changes to the FW program itself
2. CSS header size field was fixed
3. DMCheader length field is mentioned in dwords instead of bytes
4. Date field is fixed in header.
4. Fixed the DMC Header.HeaderLen issue. The HeaderLen is specified in bytes instead of dwords.
6. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.16
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions:
1. The DE_RRMR and DE_GUCRMR register bits are set before the restore of
the registers to mask the flip done, etc. Once all the registers are
restored, these registers are restored.
2. The pipe interrupt registers are restored only after the plane has
been enabled.
3. Naming of the file changed from .5 to .16 to make it two decimal
points for increased number of versions that can be supported.
4. DC 5 and 6 count locations are in the below mentioned offsets
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
DMC provides additional graphics low-power idle states. It provides
capability to save and restore display registers across these
low-power states independently from the OS/Kernel.
This is the first release of DMC firmware for Broxton platforms.
bxt_dmc_ver1.bin is a symbolik link to latest recommended minor
release.
This major version will be just upgraded on code when it is required
software changes for API/ABI compatibility.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
GuC is designed to perform graphics workload scheduling on the various
graphics parallel engines. In this scheduling model, host software
submits work through one of the 256 graphics doorbells and this invokes
the scheduling operation on the appropriate graphics engine. Scheduling
operations include determining which workload to run next, submitting a
workload to a command streamer, pre-empting existing workloads running
on an engine, monitoring progress and notifying host SW when work is
done.
This is the first release of GuC firmware for Skylake platforms.
skl_guc_ver1.bin is a symbolik link to latest recommended minor release.
This major version will be just upgraded on code when it is required
software changes for API/ABI compatibility.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
DMC provides additional graphics low-power idle states. It provides
capability to save and restore display registers across these low-power
states independently from the OS/Kernel.
This is the first release of DMC firmware for Skylake platforms.
skl_dmc_ver1.bin is a symbolik link to latest recommended minor release.
This major version will be just upgraded on code when it is required
software changes for API/ABI compatibility.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Rodrigo Vivi