Add initial firmware and board files for QCA99X0 hw2.0 family of chipsets.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Add initial firmware and board files for QCA6174 hw3.0 family of chipsets.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Add initial firmware and board files for QCA6174 hw2.1 family of chipsets.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Add firmware 10.2.4.70.9-2 which uses FW API 5 so use name firmware-5.bin. Keep
firmware-4.bin for backwards compatibility with older ath10k versions.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
In commit 40d14143b7 ("ath10k: add firmware 10.2.4.45 as firmware-4.bin") I
forgot to commit board.bin file and that's why it was not included in the
commit even I had added an entry to WHENCE. Add that now.
At the same time also add Version field for firmware-4.bin.
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
This makes it easier for downstream distributors to check which files
are clearly distributable without unusual restrictions.
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
These files were previously available from
ftp://ftp.qlogic.com/outgoing/linux/firmware under a BSD-ish licence.
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
This patch adds the firmware patch for Intel Bluetooth 7265 (D1)
also known as Intel StP D1.
D1 Patch Version: 9
Release Version: 153.1
Signed-off-by: Tedd Ho-Jeong An <tedd.an@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This patch adds a firmware for the USB 3.0 host controllers of Renesas
R-Car H3 SoC.
This firmware is possible to use on R-Car H2 and M2. However, this
version causes performance degradation on R-Car H2 and M2. So, we would
like to keep the v1 firmware.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This patch updates the firmware patch for Intel Bluetooth 7265 (C0/D0)
also known as Intel StP C0 and StP D0.
C0 Patch Version: 54
D0 Patch Version: 28
Release Version: 153
Signed-off-by: Tedd Ho-Jeong An <tedd.an@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This patch updates the firmware patch for Intel Bluetooth 7260 (B5/B6)
also known as Intel WP2 B5 and WP1 B6
Patch Version: 34
Release Version: 153
Signed-off-by: Tedd Ho-Jeong An <tedd.an@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This patch updates the firmware patch for Intel Bluetooth 7260 (B3/B4)
also known as Intel WP2 B3 and WP1 B4
Patch Version: 83
Release Version: 153
Signed-off-by: Tedd Ho-Jeong An <tedd.an@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This patch adds firmware for Keystone QMSS Accumulator PDSP. This is required
to support Accumulator queues. Accumulator queues are one of the queue types
supported in drivers/soc/ti/knav_qmss_acc.c. This queue can be part of a
channel that supports one queue or multiple queue per channel and are managed
by the Accumulator PDSP. For more details on hardware, please refer
http://www.ti.com/lit/ug/sprugr9h/sprugr9h.pdf and DT documentation below in
linux kernel source tree
Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
The code points to the major version that is a link to the most
recent one, so we can remove the old firmware blobs.
For tests and validation purposes we will let few minor versions
available, but we need to let linux-firmware repo as
clean as possible, so let's remove old and unused ones.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Version: 1.22
Date : 9/23/2015
Notes:
Following additions from ver1.21
1. PLL lock wait time updated
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.21
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from previous version
1. Updated FW for NV12 enabling
2. Changes to the waits times for pll enable and disable.
3. Fixed GT interrupts issue
4. DC3_DC5_COUNT: 80038
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
VI asics are supported by the new amdgpu driver and
this adds the initial firmware to support them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This is the first release of the Intel OPA hfi1 firmware required by the hfi1
driver.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Steve Vogel <steve.vogel@intel.com>
Following additions from ver1:
1. Performance Improvement.
2. Fix reset issue.
3. Scheduler fix.
4. Merge in new power management features.
5. Firmware layout changes.
6. Force Fence WA to guarantee correct ordering of GTT writes from uKernel.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
The code points to the major version that is a link to the most
recent one, so we can remove the old firmware blobs.
For tests and validation purposes we will let at least 3 latest
minor available, but we need to let linux-firmware repo as
clean as possible, so let's remove old and unused ones.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.20
1. Fixed GT interrupts issue when DC6 is enabled
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.20
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.19
1. Changes to the waits times for pll enable and disable.
2. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.19
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions from ver1.04
1. No changes to the FW program itself
2. CSS header size field was fixed
3. Date field is fixed in header.
4. DC3_DC5_COUNT � 80038
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Following additions:
1. Updated FW for NV12 enabling
3. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.18 and ver1.17
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This is new firmware for wilc1000 which is a single chip IEEE 802.11
b/g/n device.
Signed-off-by: Johnny Kim <johnny.kim@atmel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
After enabling asymmetric key encryption in qat driver an update to existing
firmware is required plus a new Modular Math Processor(MMP) firmware.
This has dependency on these commits:
commit f3dd7e60d2028b8391dea7a3b214e3083dadf6d6
commit 28cfaf67e5c1f5b6b0d549eea398f8401a40e566
commit a990532023b903b10cf14736241cdd138e4bc92c
Signed-off-by: Xiaoyan Bo <xiaoyan.bo@intel.com>
Signed-off-by: Gokhan Simsek <gokhan.simsek@intel.com>
Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
The new FW will allow us to utilize some new features in our driver,
mainly adding vlan stripping offload and vxlan offload support.
In addition, this fixes several issues:
- Packets from a VF with pvid configured which were sent with a
different vlan were transmitted instead of being discarded.
- FCoE traffic might not recover after a failue while there's traffic
to another function.
Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This updates the firmware for BSW platform, which includes the fixes for BSW
power management.
The firmware version is also added to WHENCE file. The version is
v01.0B.02.01.
The md5sum of the file is cf8caa8d33e95744f25adcab1373daff
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
Latest firmware files supporting QCA61x4 ROME family chipset
Signed-off-by: Ben Young Tae Kim <ytkim@qca.qualcomm.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
The atusb kernel driver is sitting in the bluetooth-next tree waiting for the
merge window to open. It's scheduled for 4.2.
Flashing goes into permanent storage and the GPLv2+ firmware allows for further
explorations. See ChangeLog for more details and links.
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
This is the firmware for the VCE (video encoding engine)
block in SI and TN/RL asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kyle McMartin <kyle@kernel.org>
Following additions:
1. No changes to the FW program itself
2. CSS header size field was fixed
3. DMCheader length field is mentioned in dwords instead of bytes
4. Date field is fixed in header.
4. Fixed the DMC Header.HeaderLen issue. The HeaderLen is specified in bytes instead of dwords.
6. DC 5 and 6 count locations are in the below mentioned offsets - same as ver1.16
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This firmware also supports 3165.
This is the first firmware release for 8000.
Version number: 25.30.13.0
Revision number: 183742
Build number: WFFW14681
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Following additions:
1. The DE_RRMR and DE_GUCRMR register bits are set before the restore of
the registers to mask the flip done, etc. Once all the registers are
restored, these registers are restored.
2. The pipe interrupt registers are restored only after the plane has
been enabled.
3. Naming of the file changed from .5 to .16 to make it two decimal
points for increased number of versions that can be supported.
4. DC 5 and 6 count locations are in the below mentioned offsets
DC3_DC5_COUNT 80030
DC5_DC6_COUNT 8002C
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
DMC provides additional graphics low-power idle states. It provides
capability to save and restore display registers across these
low-power states independently from the OS/Kernel.
This is the first release of DMC firmware for Broxton platforms.
bxt_dmc_ver1.bin is a symbolik link to latest recommended minor
release.
This major version will be just upgraded on code when it is required
software changes for API/ABI compatibility.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
GuC is designed to perform graphics workload scheduling on the various
graphics parallel engines. In this scheduling model, host software
submits work through one of the 256 graphics doorbells and this invokes
the scheduling operation on the appropriate graphics engine. Scheduling
operations include determining which workload to run next, submitting a
workload to a command streamer, pre-empting existing workloads running
on an engine, monitoring progress and notifying host SW when work is
done.
This is the first release of GuC firmware for Skylake platforms.
skl_guc_ver1.bin is a symbolik link to latest recommended minor release.
This major version will be just upgraded on code when it is required
software changes for API/ABI compatibility.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
David Lin