A better-scheduled PPC SHA-1 implementation.
This is about 15% faster that the current sha1ppc.S on a G4, and 5% faster on a G5 when hashing 10 million bytes, unaligned. (The G5 ratio seems to get better as the sizes fall.) It's also somewhat smaller, due to using load-multiple instructions. No copyright is claimed on the changes to Paul Mackerras' work below.maint
Unknown
Junio C Hamano
parent
b57cbbf8a8
commit
84702995f8
327
ppc/sha1ppc.S
327
ppc/sha1ppc.S
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@ -3,183 +3,222 @@
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*
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*
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* Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
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* Copyright (C) 2005 Paul Mackerras <paulus@samba.org>
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*/
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*/
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#define FS 80
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/*
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/*
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* We roll the registers for T, A, B, C, D, E around on each
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* PowerPC calling convention:
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* iteration; T on iteration t is A on iteration t+1, and so on.
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* %r0 - volatile temp
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* We use registers 7 - 12 for this.
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* %r1 - stack pointer.
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* %r2 - reserved
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* %r3-%r12 - Incoming arguments & return values; volatile.
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* %r13-%r31 - Callee-save registers
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* %lr - Return address, volatile
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* %ctr - volatile
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*
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* Register usage in this routine:
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* %r0 - temp
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* %r3 - argument (pointer to 5 words of SHA state)
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* %r4 - argument (pointer to data to hash)
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* %r5 - Contant K in SHA round (initially number of blocks to hash)
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* %r6-%r10 - Working copies of SHA variables A..E (actually E..A order)
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* %r11-%r26 - Data being hashed W[].
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* %r27-%r31 - Previous copies of A..E, for final add back.
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* %ctr - loop count
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*/
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*/
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#define RT(t) ((((t)+5)%6)+7)
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#define RA(t) ((((t)+4)%6)+7)
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#define RB(t) ((((t)+3)%6)+7)
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#define RC(t) ((((t)+2)%6)+7)
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#define RD(t) ((((t)+1)%6)+7)
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#define RE(t) ((((t)+0)%6)+7)
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/* We use registers 16 - 31 for the W values */
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#define W(t) (((t)%16)+16)
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#define STEPD0(t) \
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/*
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and %r6,RB(t),RC(t); \
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* We roll the registers for A, B, C, D, E around on each
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andc %r0,RD(t),RB(t); \
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* iteration; E on iteration t is D on iteration t+1, and so on.
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rotlwi RT(t),RA(t),5; \
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* We use registers 6 - 10 for this. (Registers 27 - 31 hold
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rotlwi RB(t),RB(t),30; \
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* the previous values.)
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or %r6,%r6,%r0; \
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*/
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add %r0,RE(t),%r15; \
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#define RA(t) (((t)+4)%5+6)
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add RT(t),RT(t),%r6; \
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#define RB(t) (((t)+3)%5+6)
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add %r0,%r0,W(t); \
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#define RC(t) (((t)+2)%5+6)
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add RT(t),RT(t),%r0
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#define RD(t) (((t)+1)%5+6)
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#define RE(t) (((t)+0)%5+6)
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#define STEPD1(t) \
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/* We use registers 11 - 26 for the W values */
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xor %r6,RB(t),RC(t); \
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#define W(t) ((t)%16+11)
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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xor %r6,%r6,RD(t); \
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add %r0,RE(t),%r15; \
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add RT(t),RT(t),%r6; \
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add %r0,%r0,W(t); \
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add RT(t),RT(t),%r0
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#define STEPD2(t) \
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/* Register 5 is used for the constant k */
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and %r6,RB(t),RC(t); \
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and %r0,RB(t),RD(t); \
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rotlwi RT(t),RA(t),5; \
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rotlwi RB(t),RB(t),30; \
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or %r6,%r6,%r0; \
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and %r0,RC(t),RD(t); \
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or %r6,%r6,%r0; \
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add %r0,RE(t),%r15; \
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add RT(t),RT(t),%r6; \
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add %r0,%r0,W(t); \
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add RT(t),RT(t),%r0
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#define LOADW(t) \
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/*
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lwz W(t),(t)*4(%r4)
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* The basic SHA-1 round function is:
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* E += ROTL(A,5) + F(B,C,D) + W[i] + K; B = ROTL(B,30)
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* Then the variables are renamed: (A,B,C,D,E) = (E,A,B,C,D).
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*
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* Every 20 rounds, the function F() and the contant K changes:
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* - 20 rounds of f0(b,c,d) = "bit wise b ? c : d" = (^b & d) + (b & c)
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* - 20 rounds of f1(b,c,d) = b^c^d = (b^d)^c
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* - 20 rounds of f2(b,c,d) = majority(b,c,d) = (b&d) + ((b^d)&c)
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* - 20 more rounds of f1(b,c,d)
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*
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* These are all scheduled for near-optimal performance on a G4.
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* The G4 is a 3-issue out-of-order machine with 3 ALUs, but it can only
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* *consider* starting the oldest 3 instructions per cycle. So to get
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* maximum performace out of it, you have to treat it as an in-order
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* machine. Which means interleaving the computation round t with the
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* computation of W[t+4].
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*
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* The first 16 rounds use W values loaded directly from memory, while the
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* remianing 64 use values computed from those first 16. We preload
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* 4 values before starting, so there are three kinds of rounds:
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* - The first 12 (all f0) also load the W values from memory.
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* - The next 64 compute W(i+4) in parallel. 8*f0, 20*f1, 20*f2, 16*f1.
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* - The last 4 (all f1) do not do anything with W.
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*
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* Therefore, we have 6 different round functions:
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* STEPD0_LOAD(t,s) - Perform round t and load W(s). s < 16
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* STEPD0_UPDATE(t,s) - Perform round t and compute W(s). s >= 16.
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* STEPD1_UPDATE(t,s)
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* STEPD2_UPDATE(t,s)
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* STEPD1(t) - Perform round t with no load or update.
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*
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* The G5 is more fully out-of-order, and can find the parallelism
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* by itself. The big limit is that it has a 2-cycle ALU latency, so
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* even though it's 2-way, the code has to be scheduled as if it's
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* 4-way, which can be a limit. To help it, we try to schedule the
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* read of RA(t) as late as possible so it doesn't stall waiting for
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* the previous round's RE(t-1), and we try to rotate RB(t) as early
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* as possible while reading RC(t) (= RB(t-1)) as late as possible.
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*/
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#define UPDATEW(t) \
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/* the initial loads. */
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xor %r0,W((t)-3),W((t)-8); \
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#define LOADW(s) \
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xor W(t),W((t)-16),W((t)-14); \
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lwz W(s),(s)*4(%r4)
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xor W(t),W(t),%r0; \
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rotlwi W(t),W(t),1
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#define STEP0LD4(t) \
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/*
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STEPD0(t); LOADW((t)+4); \
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* Perform a step with F0, and load W(s). Uses W(s) as a temporary
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STEPD0((t)+1); LOADW((t)+5); \
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* before loading it.
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STEPD0((t)+2); LOADW((t)+6); \
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* This is actually 10 instructions, which is an awkward fit.
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STEPD0((t)+3); LOADW((t)+7)
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* It can execute grouped as listed, or delayed one instruction.
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* (If delayed two instructions, there is a stall before the start of the
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* second line.) Thus, two iterations take 7 cycles, 3.5 cycles per round.
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*/
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#define STEPD0_LOAD(t,s) \
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add RE(t),RE(t),W(t); andc %r0,RD(t),RB(t); and W(s),RC(t),RB(t); \
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add RE(t),RE(t),%r0; rotlwi %r0,RA(t),5; rotlwi RB(t),RB(t),30; \
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add RE(t),RE(t),W(s); add %r0,%r0,%r5; lwz W(s),(s)*4(%r4); \
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add RE(t),RE(t),%r0
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#define STEPUP4(t, fn) \
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/*
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STEP##fn(t); UPDATEW((t)+4); \
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* This is likewise awkward, 13 instructions. However, it can also
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STEP##fn((t)+1); UPDATEW((t)+5); \
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* execute starting with 2 out of 3 possible moduli, so it does 2 rounds
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STEP##fn((t)+2); UPDATEW((t)+6); \
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* in 9 cycles, 4.5 cycles/round.
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STEP##fn((t)+3); UPDATEW((t)+7)
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*/
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#define STEPD0_UPDATE(t,s,loadk...) \
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add RE(t),RE(t),W(t); andc %r0,RD(t),RB(t); xor W(s),W((s)-16),W((s)-3); \
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add RE(t),RE(t),%r0; and %r0,RC(t),RB(t); xor W(s),W(s),W((s)-8); \
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add RE(t),RE(t),%r0; rotlwi %r0,RA(t),5; xor W(s),W(s),W((s)-14); \
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add RE(t),RE(t),%r5; loadk; rotlwi RB(t),RB(t),30; rotlwi W(s),W(s),1; \
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add RE(t),RE(t),%r0
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#define STEPUP20(t, fn) \
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/* Nicely optimal. Conveniently, also the most common. */
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STEPUP4(t, fn); \
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#define STEPD1_UPDATE(t,s,loadk...) \
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STEPUP4((t)+4, fn); \
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add RE(t),RE(t),W(t); xor %r0,RD(t),RB(t); xor W(s),W((s)-16),W((s)-3); \
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STEPUP4((t)+8, fn); \
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add RE(t),RE(t),%r5; loadk; xor %r0,%r0,RC(t); xor W(s),W(s),W((s)-8); \
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STEPUP4((t)+12, fn); \
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add RE(t),RE(t),%r0; rotlwi %r0,RA(t),5; xor W(s),W(s),W((s)-14); \
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STEPUP4((t)+16, fn)
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add RE(t),RE(t),%r0; rotlwi RB(t),RB(t),30; rotlwi W(s),W(s),1
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/*
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* The naked version, no UPDATE, for the last 4 rounds. 3 cycles per.
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* We could use W(s) as a temp register, but we don't need it.
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*/
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#define STEPD1(t) \
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add RE(t),RE(t),W(t); xor %r0,RD(t),RB(t); \
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rotlwi RB(t),RB(t),30; add RE(t),RE(t),%r5; xor %r0,%r0,RC(t); \
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add RE(t),RE(t),%r0; rotlwi %r0,RA(t),5; /* spare slot */ \
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add RE(t),RE(t),%r0
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/*
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* 14 instructions, 5 cycles per. The majority function is a bit
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* awkward to compute. This can execute with a 1-instruction delay,
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* but it causes a 2-instruction delay, which triggers a stall.
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*/
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#define STEPD2_UPDATE(t,s,loadk...) \
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add RE(t),RE(t),W(t); and %r0,RD(t),RB(t); xor W(s),W((s)-16),W((s)-3); \
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add RE(t),RE(t),%r0; xor %r0,RD(t),RB(t); xor W(s),W(s),W((s)-8); \
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add RE(t),RE(t),%r5; loadk; and %r0,%r0,RC(t); xor W(s),W(s),W((s)-14); \
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add RE(t),RE(t),%r0; rotlwi %r0,RA(t),5; rotlwi W(s),W(s),1; \
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add RE(t),RE(t),%r0; rotlwi RB(t),RB(t),30
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#define STEP0_LOAD4(t,s) \
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STEPD0_LOAD(t,s); \
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STEPD0_LOAD((t+1),(s)+1); \
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STEPD0_LOAD((t)+2,(s)+2); \
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STEPD0_LOAD((t)+3,(s)+3)
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#define STEPUP4(fn, t, s, loadk...) \
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STEP##fn##_UPDATE(t,s,); \
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STEP##fn##_UPDATE((t)+1,(s)+1,); \
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STEP##fn##_UPDATE((t)+2,(s)+2,); \
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STEP##fn##_UPDATE((t)+3,(s)+3,loadk)
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#define STEPUP20(fn, t, s, loadk...) \
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STEPUP4(fn, t, s,); \
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STEPUP4(fn, (t)+4, (s)+4,); \
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STEPUP4(fn, (t)+8, (s)+8,); \
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STEPUP4(fn, (t)+12, (s)+12,); \
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STEPUP4(fn, (t)+16, (s)+16, loadk)
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.globl sha1_core
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.globl sha1_core
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sha1_core:
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sha1_core:
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stwu %r1,-FS(%r1)
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stwu %r1,-80(%r1)
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stw %r15,FS-68(%r1)
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stmw %r13,4(%r1)
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stw %r16,FS-64(%r1)
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stw %r17,FS-60(%r1)
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stw %r18,FS-56(%r1)
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stw %r19,FS-52(%r1)
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stw %r20,FS-48(%r1)
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stw %r21,FS-44(%r1)
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stw %r22,FS-40(%r1)
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stw %r23,FS-36(%r1)
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stw %r24,FS-32(%r1)
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stw %r25,FS-28(%r1)
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stw %r26,FS-24(%r1)
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stw %r27,FS-20(%r1)
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stw %r28,FS-16(%r1)
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stw %r29,FS-12(%r1)
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stw %r30,FS-8(%r1)
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stw %r31,FS-4(%r1)
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/* Load up A - E */
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/* Load up A - E */
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lwz RA(0),0(%r3) /* A */
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lmw %r27,0(%r3)
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lwz RB(0),4(%r3) /* B */
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lwz RC(0),8(%r3) /* C */
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lwz RD(0),12(%r3) /* D */
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lwz RE(0),16(%r3) /* E */
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mtctr %r5
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mtctr %r5
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1: LOADW(0)
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1:
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LOADW(0)
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lis %r5,0x5a82
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mr RE(0),%r31
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LOADW(1)
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LOADW(1)
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mr RD(0),%r30
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mr RC(0),%r29
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LOADW(2)
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LOADW(2)
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ori %r5,%r5,0x7999 /* K0-19 */
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mr RB(0),%r28
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LOADW(3)
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LOADW(3)
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mr RA(0),%r27
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lis %r15,0x5a82 /* K0-19 */
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STEP0_LOAD4(0, 4)
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ori %r15,%r15,0x7999
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STEP0_LOAD4(4, 8)
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STEP0LD4(0)
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STEP0_LOAD4(8, 12)
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STEP0LD4(4)
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STEPUP4(D0, 12, 16,)
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STEP0LD4(8)
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STEPUP4(D0, 16, 20, lis %r5,0x6ed9)
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STEPUP4(12, D0)
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STEPUP4(16, D0)
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lis %r15,0x6ed9 /* K20-39 */
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ori %r5,%r5,0xeba1 /* K20-39 */
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ori %r15,%r15,0xeba1
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STEPUP20(D1, 20, 24, lis %r5,0x8f1b)
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STEPUP20(20, D1)
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lis %r15,0x8f1b /* K40-59 */
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ori %r5,%r5,0xbcdc /* K40-59 */
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ori %r15,%r15,0xbcdc
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STEPUP20(D2, 40, 44, lis %r5,0xca62)
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STEPUP20(40, D2)
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lis %r15,0xca62 /* K60-79 */
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ori %r5,%r5,0xc1d6 /* K60-79 */
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ori %r15,%r15,0xc1d6
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STEPUP4(D1, 60, 64,)
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STEPUP4(60, D1)
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STEPUP4(D1, 64, 68,)
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STEPUP4(64, D1)
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STEPUP4(D1, 68, 72,)
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STEPUP4(68, D1)
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STEPUP4(D1, 72, 76,)
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STEPUP4(72, D1)
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addi %r4,%r4,64
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STEPD1(76)
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STEPD1(76)
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STEPD1(77)
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STEPD1(77)
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STEPD1(78)
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STEPD1(78)
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STEPD1(79)
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STEPD1(79)
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lwz %r20,16(%r3)
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/* Add results to original values */
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lwz %r19,12(%r3)
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add %r31,%r31,RE(0)
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lwz %r18,8(%r3)
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add %r30,%r30,RD(0)
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lwz %r17,4(%r3)
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add %r29,%r29,RC(0)
|
||||||
lwz %r16,0(%r3)
|
add %r28,%r28,RB(0)
|
||||||
add %r20,RE(80),%r20
|
add %r27,%r27,RA(0)
|
||||||
add RD(0),RD(80),%r19
|
|
||||||
add RC(0),RC(80),%r18
|
|
||||||
add RB(0),RB(80),%r17
|
|
||||||
add RA(0),RA(80),%r16
|
|
||||||
mr RE(0),%r20
|
|
||||||
stw RA(0),0(%r3)
|
|
||||||
stw RB(0),4(%r3)
|
|
||||||
stw RC(0),8(%r3)
|
|
||||||
stw RD(0),12(%r3)
|
|
||||||
stw RE(0),16(%r3)
|
|
||||||
|
|
||||||
addi %r4,%r4,64
|
|
||||||
bdnz 1b
|
bdnz 1b
|
||||||
|
|
||||||
lwz %r15,FS-68(%r1)
|
/* Save final hash, restore registers, and return */
|
||||||
lwz %r16,FS-64(%r1)
|
stmw %r27,0(%r3)
|
||||||
lwz %r17,FS-60(%r1)
|
lmw %r13,4(%r1)
|
||||||
lwz %r18,FS-56(%r1)
|
addi %r1,%r1,80
|
||||||
lwz %r19,FS-52(%r1)
|
|
||||||
lwz %r20,FS-48(%r1)
|
|
||||||
lwz %r21,FS-44(%r1)
|
|
||||||
lwz %r22,FS-40(%r1)
|
|
||||||
lwz %r23,FS-36(%r1)
|
|
||||||
lwz %r24,FS-32(%r1)
|
|
||||||
lwz %r25,FS-28(%r1)
|
|
||||||
lwz %r26,FS-24(%r1)
|
|
||||||
lwz %r27,FS-20(%r1)
|
|
||||||
lwz %r28,FS-16(%r1)
|
|
||||||
lwz %r29,FS-12(%r1)
|
|
||||||
lwz %r30,FS-8(%r1)
|
|
||||||
lwz %r31,FS-4(%r1)
|
|
||||||
addi %r1,%r1,FS
|
|
||||||
blr
|
blr
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue