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A number of platforms have a need to reduce the number of DT nodes, mostly because of two similar constraints: the size of the DT blob, and the time it takes to parse it. As the DT is used in more and more SoCs, and by more projects, some constraints start to appear in bootloaders running from SRAM with an order of magnitude of 10kB. A typical DT is in the same order of magnitude, so any effort to reduce the blob size is welcome in such an environment. Some platforms also want to reach very fast boot time, and the time it takes to parse a typical DT starts to be noticeable. Both of these issues can be mitigated by reducing the number of nodes in the DT. The biggest provider of nodes is usually the pin controller and its subnodes, usually one for each valid pin configuration in a given SoC. Obviously, a single, fixed, set of these nodes will be used by a given board, so we can introduce a node property that will tell the DT compiler to drop the nodes when they are not referenced in the tree, and as such wouldn't be useful in the targetted system. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>main
Maxime Ripard
7 years ago
committed by
David Gibson
5 changed files with 55 additions and 0 deletions
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